A method and device for saving resource overhead by using time slot arbitration

Abstract

The invention discloses a method and equipment for saving resource overhead by using time slot arbitration. The method is applied to a programmable logic array FPGA logic chip, and the FPGA logic chip includes N receiving modules with identical processing functions and a scheduling module SCH , N receiving modules receive data through their respective IF interfaces, and write it into the first-in-first-out DATAQ buffer; N receiving modules read B-bit data from the DATAQ buffer per time slot through their respective SELECT sub-function modules, and write Into the data memory BUFFER of SCH, the BUFFER is realized by splicing M blocks of RAM, the M blocks of RAM are sequentially numbered, and each block of RAM is divided into address spaces, and the address space of each block of RAM is sequentially numbered, and the time slot is determined by the TIMERSLOT of SCH Assignment, the cycle is N; SCH reads data from BUFFER through the MAC submodule, processes it, and sends it out; the MAC submodule reads M blocks of RAM at the same time each time, and each block of RAM reads an address space, and The address space numbers of M blocks of RAM for reading data are the same.

Description

technical field [0001] The invention relates to network communication transmission technology, in particular to a method and equipment for saving resource overhead by using time slot arbitration. Background technique [0002] In the application of communication technology, it often involves the need to perform functional processing on multiple interfaces or modules, and the methods of these functional processing modules are the same. [0003] For example, if a chip is connected with 32 E1 ports, the functions of these E1 ports are the same; for another example, a chip is connected with 16 Gigabit Ethernet ports (GE, gigabit ethernet), and the processing functions of these GE ports are also the same. [0004] In the initial implementation, multiple identical processing function modules were used to realize it; as the chip function is optimized and implemented, it is necessary to consider implementing these interface modules with the same function as a high-bandwidth functiona...

AI Technical Summary

Problems solved by technology

[0008] The RR polling module needs to read data from 16 receiving interfaces, the processing is quite complicated, the hardware timing is also difficult to run, and the resources are also consumed due to the bus bit width.

[0009] Due to the wide bit width of the random access memory RAM of the receiving module, multiple RAMs are required to be spliced ​​to realize a 256-bit wide RAM, and the FIFO of each MAC receiving data does not play the role of buffering and absorbing, resulting in the consumption of a lot of RAM resources

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