An Optimized Instruction Scheduling and Register Allocation Method on Clustered VLIW Processor

A technology for register allocation and instruction scheduling, applied in resource allocation, concurrent instruction execution, machine execution devices, etc., can solve the problem of increasing basic block scheduling time, achieve the effect of reducing register overflow and optimizing performance

Active Publication Date: 2017-12-26
NAT UNIV OF DEFENSE TECH
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Problems solved by technology

Third, improper inter-cluster instruction allocation can lead to unnecessary inter-cluster communication, which increases the scheduling time of basic blocks

Method used

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  • An Optimized Instruction Scheduling and Register Allocation Method on Clustered VLIW Processor
  • An Optimized Instruction Scheduling and Register Allocation Method on Clustered VLIW Processor
  • An Optimized Instruction Scheduling and Register Allocation Method on Clustered VLIW Processor

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Embodiment Construction

[0031] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0032] Such as figure 1 As shown, the instruction scheduling and register allocation method on a kind of optimized sub-clustering VLIW processor of the present invention aims at minimizing the longest execution time of the program, and it includes two stages: in the first stage, using a unified The algorithm performs the first pass of instruction scheduling and register allocation for all basic blocks; in the second stage, according to the length of the longest path to which the basic block belongs and the highest execution frequency, instruction rescheduling and register rescheduling are performed on the basic blocks with register overflow. distribute.

[0033] During specific application, the detailed flow process of the present invention is:

[0034] (1) Construct the authorized control flow graph G of program P, where w i undef...

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Abstract

The invention discloses an optimized instruction scheduling and register allocation method on a clustered VLIW processor, which includes two stages: in the first stage, a unified algorithm is used to perform the first-pass instruction scheduling and register allocation for all basic blocks ; In the second stage, according to the length of the longest path to which the basic block belongs and the highest execution frequency, perform instruction rescheduling and register reallocation on the basic block with register overflow. The invention has the advantages of wide application range, good performance optimization effect, can effectively reduce the longest execution time of the program in the real-time system, and the like.

Description

technical field [0001] The invention mainly relates to the technical field of processor compilation optimization, in particular to an optimized instruction scheduling and register allocation method suitable for clustered VLIW processors. Background technique [0002] The longest execution time of the program is one of the important bases to measure the design of embedded real-time system, and all time constraints must be met to ensure the correctness of the real-time system. The maximum execution time of a program has a significant impact on assigning a feasible schedule to the program. The running time of the program is different because different branches may be executed during the running of the program, and the longest running time of the program refers to the longest running time of the program on the target platform. A program cannot be assigned a feasible schedule if its maximum execution time is greater than the time limit of the real-time system. If the maximum ex...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/38G06F9/50
Inventor 张雪萌吴辉孙海燕王霁阳柳郭阳扈啸
Owner NAT UNIV OF DEFENSE TECH
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