Unlock instant, AI-driven research and patent intelligence for your innovation.

Cache memory controller and method for controlling cache memory

A memory controller and cache technology, applied in memory systems, instruments, memory architecture access/allocation, etc., can solve the problems of speedup, increased power consumption, low waiting time, etc., to achieve the effect of cache hits

Inactive Publication Date: 2015-04-08
MITSUBISHI ELECTRIC CORP
View PDF4 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This results in a slowdown in speed and an increase in power consumption due to the waiting time for program generation

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Cache memory controller and method for controlling cache memory
  • Cache memory controller and method for controlling cache memory
  • Cache memory controller and method for controlling cache memory

Examples

Experimental program
Comparison scheme
Effect test

Embodiment approach 1

[0048] figure 1 It is a block diagram schematically showing the configuration of the cache memory controller 100 according to the first embodiment. The cache memory controller 100 has a cache memory 110 , a memory management unit 120 , a hit detection unit 130 , and a data processing unit 140 .

[0049] exist figure 1In , the connection relationship among the access host 1, the cache memory controller 100, and the main memory 10 is simply shown. The cache memory controller 100 performs access to data stored in the cache memory 110 or the main memory 10 described later in accordance with the command C1 from the access host 1 . Here, the command command C1 is an access request from the access host 1 to an address on the main memory 10 . For example, if the command C1 is a read request, the access host 1 inputs the command C1 and the command address A1 indicating an address on the main memory 10 to the cache memory controller 100 . Then, the cache memory controller 100 output...

Embodiment approach 2

[0137] according to Figure 16 ~ Figure 30 , Embodiment 2 will be described.

[0138] Figure 16 It is a block diagram schematically showing the configuration of the cache memory controller 200 according to the second embodiment. The cache memory controller 200 has a cache memory 110 , a memory management unit 120 , a hit detection unit 130 , and a data processing unit 240 .

[0139] exist Figure 16 In , the connection relationship between the access host 1, the cache memory controller 200, and the main memory 10 is simply shown.

[0140] The main memory 10 is collectively managed by a certain capacity called a bank. The segment is divided into a command area and a data area. In addition, with respect to the main memory 10, by specifying a row (Row) address and a column (Column) address, a specific continuous area can be accessed.

[0141] The functions of the cache memory 110 , the memory management unit 120 , and the hit detection unit 130 are the same as those in Emb...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

Provided is a cache memory controller (100) connected to a main memory (10) having an instruction area for storing a first program, and a data area for storing data used by instructions included in the first program, and to an access master (1) for executing instructions included in the first program, wherein the controller is provided with: a cache memory (110) for storing a portion of the data in the main memory (10); and a data processing unit (140) that, prior to execution of a specific instruction by the access master (1), and in accordance with transfer scheduling information contained in the beginning address of the specific instruction, calculates an access interval on the basis of the number of instruction steps remaining from the address of the instruction currently being executed by the access master (1), to the beginning address of the specific instruction; and during this access interval, transfers data to be used by the specific instruction from the main memory (10) to the cache memory (110).

Description

technical field [0001] The present invention relates to a cache memory controller and a cache memory control method. Background technique [0002] In recent years, the amount of data such as computer programs and videos handled by devices has been increasing, and the capacity of hard disks and main memories mounted in devices has also increased. The main memory is divided into a command area and a data area. Commands such as programs are stored in the command area, and data such as video used for processing these commands are stored in the data area. The operating frequency of the main memory is lower than that of a CPU and the like for accessing a host, and therefore, a cache memory (cache memory) capable of high-speed access is generally used. The accessing host can perform higher-speed data reading and writing by accessing the cache memory. [0003] However, a cache memory has a small capacity per unit area and is expensive, so it is often difficult to replace the enti...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/08G06F12/0862G06F12/0875
CPCG06F12/0862G06F2212/6028G06F12/0875G06F2212/1024G06F2212/452
Inventor 田中沙织贵岛淳子内藤正博
Owner MITSUBISHI ELECTRIC CORP