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Phase change memory management method and phase change memory management apparatus

A phase-change memory and management method technology, applied in information storage, static memory, digital memory information and other directions, can solve the problem of large write operation time delay, and achieve the effect of reducing time delay and avoiding long writing time.

Active Publication Date: 2015-04-15
HUAWEI TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

It can solve the problem of large write operation time delay in the phase change memory in the prior art

Method used

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  • Phase change memory management method and phase change memory management apparatus
  • Phase change memory management method and phase change memory management apparatus
  • Phase change memory management method and phase change memory management apparatus

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Embodiment Construction

[0048] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

[0049] see figure 1 , is a schematic flowchart of a phase-change memory management method according to the first embodiment of the present invention. In this embodiment, the method includes:

[0050] S101. Query free pages in the phase change memory.

[0051] Specifically, the free page refers to an unoccupied physical page in the phase change memory. When the operating system needs to run a process, the CPU will allocate a section of unoccupied physic...

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Abstract

An embodiment in the invention discloses a phase change memory management method comprises following steps: (1) querying a free page in a phase change memory; (2) performing a 1-filling operation to each bit in the free page to generate a filled page; (3) when a write operation to the filled page is received, determining a bit address required to be 0-filled in the filled page according to the write operation; and (4) performing 0-writing to the bit corresponding to the bit address. The embodiment also discloses a phase change memory management apparatus. By means of the method and the apparatus, when the write operation to the filled page is carried out, only is 0 required to be written to the filled page while 1 is not required to be written so that a problem of a long required time during 1-writing to a memory page in the prior art is avoided. The method and the apparatus can effectively reduce time delay during the write operation.

Description

technical field [0001] The invention relates to the field of computers, in particular to a phase change memory management method and device. Background technique [0002] As a new generation of NVM storage medium, PCM (Phase Change Memory) has the characteristics of short read and write delay and long life. However, the delay of PCM write operation is much longer than that of read operation. At the same time, the delay of writing 0 and writing 1 of phase change memory is asymmetrical. The delay of writing 0 is very short, and the delay of writing 1 is very long. The time difference between the two is more than ten times. [0003] The existing technology adopts the method of writing concurrently by batch, and does not distinguish between writing 0 and writing 1. In a batch of data, it is necessary to wait for all 0s and 1s in the batch of data to be written before writing the next batch. The scheme needs to wait for all the bits in the data to be written before writing the ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C13/00
Inventor 徐君
Owner HUAWEI TECH CO LTD