A method for dynamic partitioning of multi-choice regions based on fpga analytic layout solver

Abstract

The present invention relates to a method for dynamic division of multi-choice regions based on an FPGA analytic layout solver. The method includes: constructing a first cost function and calculating each The first coordinate value of the LE in the chip layout; determine the multiple overlapping areas of the LE in the chip, and find out the legal area ranges for the multiple overlapping areas; recursively divide the multiple overlapping areas in parallel; After division, the LEs in multiple overlapping areas are respectively applied with pulling force, and the LEs in each overlapping area are pulled apart; according to the connection relationship between the basic units of each LE after being pulled apart, a second cost function is constructed to generate the LEs of each LE The second coordinate value: continue to determine the overlapping area, find out the legal area range of the overlapping area, iteratively generate the Nth coordinate value of each LE, until the Nth coordinate value is the legal layout solution of each LE. In the present invention, the parallel two-division speed is fast, and the calculation speed is greatly improved.

Description

technical field [0001] The invention relates to an FPGA layout algorithm, in particular to a method for dynamically dividing multi-choice regions based on an FPGA analytic layout solver. Background technique [0002] At present, in the application of FPGA (Field Programmable Gate Array, Field Programmable Logic Gate Array), integrated circuits are required to have a programmable or configurable interconnection network, and logic gates are connected to each other through a configurable interconnection network, as an independent chip Or the FPGA that plays a role in the core part of the system has been widely used in a large number of microelectronic devices. The broad definition of FPGA logic gates not only refers to simple NAND gates, but also refers to logic units with configurable functions of combinational logic and sequential logic or logic blocks composed of multiple logic units interconnected. [0003] With the expansion of the FPGA chip scale, the layout algorithm is...

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Problems solved by technology

[0005] However, the industry has not yet proposed a good solution to the overlapping problem of the analytical algorithm. Generally, in the first iteration, the solved LE coordinates overlap a lot, and the overlap between the LEs in the last iteration is the smallest, even if it is the last Iteration cannot completely eliminate the overlap between LEs. Generally, a partial legalization process is added after the analytical algorithm. Due to the large size of the layout circuit, the processing time is too long, which often fails to meet the program running time requirements.

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