Radiation-resistant SRAM self-refresh circuit with high utilizable ratio, and self-refresh method of radiation-resistant SRAM self-refresh circuit

Abstract

The invention relates to a radiation-resistant SRAM (static random access memory) self-refresh circuit with a high utilizable ratio. The radiation-resistant self-refresh circuit comprises a timing counter, a refresh controller and a refresh address counter, wherein the output end of the timing counter is connected with the input end of the refresh controller, the output end for receiving external signals, of the refresh controller, is connected with the input end of the refresh address counter, the output end of the refresh address counter is connected with the end A , a CSN end and a WEN end of an SRAM memory array, and the end Q of the output end of the SRAM memory array is connected with the end D of the SRAM memory array through a third voting device. The invention further discloses a self-refresh method of the radiation-resistant SRAM self-refresh circuit with the high utilizable ratio. The radiation-resistant SRAM self-refresh circuit disclosed by the invention reads, corrects and rewrites a memory periodically, the situation that wrong digit numbers accumulated at a specified time interval do not exceed the correction capability of correction codes is guaranteed, and the capability of resisting multi-bit overturn, of the SRAM, is improved; the priority grade of a user is superior to the priority grade of refreshing, so that the reading-writing operation performed by the user on the SRAM cannot be interrupted by refreshing operation, and the high utilizable ratio of the reading and the writing of the user is guaranteed.

Description

technical field [0001] The invention relates to the technical field of refresh circuits, in particular to a radiation-resistant SRAM self-refresh circuit with high availability and a self-refresh method thereof. Background technique [0002] As a volatile memory SRAM for computer cache memory, it is widely used in communications and consumer electronics products. In addition, in the field of aerospace, SRAM is also widely used. However, there are a large number of high-energy particle rays in the universe and outer space, which will directly affect its reliability and cause the data stored in the SRAM device to flip. At present, based on the commercial process line, the anti-single event flipping reinforcement of the SRAM chip is mainly adopted to strengthen the circuit and system architecture optimization design for radiation resistance. The existing technologies include three-mode redundancy (Time Module Redundancy, TMR), error Detection and correction (Error detection an...

AI Technical Summary

Problems solved by technology

However, if the data stored in the SRAM is not read or written for a long time, the errors will continue to accumulate, causing more errors, and the TMR or EDAC circuit will not be able to correct the errors in the SRAM

Aeroflex's UT8ER512K32 16M SRAM and TI's SMV512K32HFG 16M SRAM radiation-resistant SRAM memory use refresh technology to solve the problem of error accumulation. However, the priority of these two circuits is higher than that of external users to read and write. Users cannot read and write to SRAM, and the interval between two refresh operations is the read and write time available to external users. In this way, when the refresh frequency increases, the availability of the memory will decrease.

Images