A radiation-resistant SRAM self-refresh circuit with high availability and its self-refresh method

Abstract

The invention relates to a radiation-resistant SRAM self-refresh circuit with high availability, including a timing counter, a refresh controller and a refresh address counter, the output end of the timing counter is connected with the input end of the refresh controller, and the refresh controller is externally connected with an external signal The output end of the refresh address counter is connected to the input end of the refresh address counter, the output end of the refresh address counter is connected to the A, CSN, and WEN ends of the SRAM memory array, and the output end Q of the SRAM memory array is connected to the D end of the SRAM memory array through the third voter. end connected. The invention also discloses a self-refresh method of a radiation-resistant SRAM self-refresh circuit with high availability. The invention regularly reads, corrects and writes back the memory, ensures that the number of error bits accumulated in a specific time interval does not exceed the error correction capability of the error correction code, and improves the anti-multi-bit flipping capability of the SRAM; the user's read and write The priority is higher than the refresh priority, so that the user's read and write operations on the SRAM will not be interrupted by the refresh operation, ensuring high availability of the user's read and write.

Description

technical field [0001] The invention relates to the technical field of refresh circuits, in particular to a high-availability anti-radiation SRAM self-refresh circuit and a self-refresh method thereof. Background technique [0002] As a volatile memory SRAM for computer cache, it is widely used in communication and consumer electronic products. In addition, in the aerospace field, SRAM also has a wide range of applications. However, there are a large number of high-energy particle rays in the universe and outer space, which will directly affect its reliability and cause the data stored in the SRAM device to be inverted. At present, SRAM chips are hardened against single-event flipping based on commercial process lines. The main method is to perform radiation hardening on circuit and system architecture optimization design. The existing technologies include Time Module Redundancy (TMR), error Detection and correction (Error detection and correction, EDAC) codec technology, e...

AI Technical Summary

Problems solved by technology

However, if the data stored in the SRAM is not read or written for a long time, the errors will continue to accumulate, causing more errors, and the TMR or EDAC circuit will not be able to correct the errors in the SRAM

Aeroflex's UT8ER512K32 16M SRAM and TI's SMV512K32HFG 16M SRAM radiation-resistant SRAM memory use refresh technology to solve the problem of error accumulation. However, the priority of these two circuits is higher than that of external users to read and write. Users cannot read and write to SRAM, and the interval between two refresh operations is the read and write time available to external users. In this way, when the refresh frequency increases, the availability of the memory will decrease.

Images