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A quantization and dequantization hardware multiplexing algorithm and hardware structure suitable for hevc standard

A hardware structure and dequantization technology, applied in the hardware multiplexing algorithm and hardware structure field of quantization and dequantization, can solve the problems of poor compression performance and achieve high performance, high-efficiency real-time encoding, and small hardware overhead

Active Publication Date: 2018-04-03
FUDAN UNIV
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Problems solved by technology

Scalar quantization is to quantize coefficients under the criterion of minimum distortion. It has better compression performance for scalar quantization in flat areas in video frames, but poor compression performance for scalar quantization in non-flat areas.

Method used

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  • A quantization and dequantization hardware multiplexing algorithm and hardware structure suitable for hevc standard
  • A quantization and dequantization hardware multiplexing algorithm and hardware structure suitable for hevc standard
  • A quantization and dequantization hardware multiplexing algorithm and hardware structure suitable for hevc standard

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Embodiment Construction

[0036] The method of the present invention will be further specifically described below in conjunction with the accompanying drawings.

[0037] The quantization and dequantization structure based on the improved algorithm described in the present invention is as follows:

[0038] figure 1 Shown is the unit for calculating the three basic parameters of q, offset, and shift. The input is the quantization step size QP, the control signal CTRL, and B is the bit depth. QP is used to determine the specific parameters of the quantization and dequantization operations; CTRL is used to control the operation Process: CTRL=0 for quantization operation, CTRL=1 for inverse quantization operation. When performing RDOQ, the quantization offset needs to be adjusted, and A1 and A2 are used to determine the compensation amount during quantization.

[0039] figure 2 Shown is the operation part of quantization and dequantization. Quantization and dequantization can be divided into four parts:...

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Abstract

The invention belongs to the technical field of high-definition digital video compression encoding and decoding, and specifically relates to a hardware multiplexing algorithm and a hardware structure suitable for quantization and inverse quantization under the HEVC video encoding standard. HEVC performs quantization with weights on the coefficients of different frequency components in the frequency domain after DCT transformation, which can reduce the number of coded symbol bits and improve image compression efficiency. Based on the quantization provisions in the HEVC standard, the present invention designs a hardware structure that can support quantization, inverse quantization, and multiplexing of quantization and inverse quantization through certain algorithm improvements. The present invention can realize higher performance with less hardware overhead, thereby efficiently realizing real-time encoding of high-definition video.

Description

technical field [0001] The invention belongs to the technical field of high-definition digital video compression encoding and decoding, and is aimed at the HEVC video encoding and decoding standard, and specifically relates to a hardware multiplexing algorithm and a hardware structure for quantization and dequantization in video encoders and decoders applicable to the HEVC video encoding standard. Background technique [0002] HEVC (High Efficiency Video Coding) is a next-generation video codec standard proposed by JCTVC, an organization jointly established by the International Telecommunications Organization (ITU) and the Motion Picture Experts Group (MPEG). The goal is to double the compression rate compared to the previous generation standard H.264 / AVC under the premise of the same visual effect. The improvement of compression ratio comes at the cost of doubling the computational complexity. [0003] Quantization plays a very important role in the lossy video compression...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04N19/42H04N19/124
Inventor 范益波谢峥黄磊磊王利鸣陆彦珩曾晓洋
Owner FUDAN UNIV
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