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Semiconductor device

A semiconductor and device technology, applied in the field of semiconductor devices, can solve the problem of low withstand voltage and achieve the effect of improving the conduction withstand voltage

Active Publication Date: 2015-05-06
RENESAS ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Therefore, the potential rise in the p-type body region cannot be sufficiently reduced by the back gate region, so there is a problem of low ON withstand voltage due to parasitic bipolar operation.

Method used

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  • Semiconductor device
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Experimental program
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Embodiment approach 1

[0051] refer to Figure 1 ~ Figure 3 , The semiconductor device of the present embodiment has, for example, an LDMOS transistor portion (a lateral insulated gate field effect transistor portion). In addition, in the semiconductor device according to the present embodiment, a so-called double resurf structure will be described as an example.

[0052] This semiconductor device mainly has a semiconductor substrate SUB, a separation insulating film SPR, and a trench gate electrode (gate electrode) TGE. Formed on the semiconductor substrate SUB with n - Drift region (drift region) NDR, p - Resurf region (first resurf region) RSF1, p - Main body area GBL, n + The source region (the first impurity region of the first conductivity type that becomes the source) SR, p + Back gate region (back gate region of the second conductivity type) PBG, n + The drain region (the second impurity region of the first conductivity type serving as the drain) DR and the n-type well region NWL.

[...

Embodiment approach 2

[0113] The semiconductor device of Embodiment 2 is mainly different from Embodiment 1 in that it has a super junction structure.

[0114] refer to Figure 27 , in this embodiment, the drain structure is composed of a superstructure structure. Specifically, in the semiconductor substrate SUB, the N columns NC containing n-type impurities and the P columns PC containing p-type impurities are formed so as to be compatible with p - The main surface S1 side of the substrate region SB is in contact. N columns NC and P columns PC are alternately arranged in a direction perpendicular to the source-drain direction. The N columns NC and the P columns PC are formed by performing multi-stage ion implantation into the semiconductor substrate SUB. The N columns NC and the P columns PC are formed with the same impurity concentration to a depth of about 3 μm from the main surface S1 . The N column NC and the P column PC are formed so that the width and the impurity concentration satisfy t...

Embodiment approach 3

[0119] The semiconductor device of Embodiment 3 is mainly different from Embodiment 1 in that the semiconductor substrate is SOI (Silicon On Insulator: silicon on insulator).

[0120] refer to Figure 29 and Figure 30 , in the semiconductor device of this embodiment mode, the insulating layer OX is formed to be the same as n - The other side of the drift region (drift region) NDR is in contact with the main surface S2 side. The insulating layer OX is made of, for example, a silicon oxide film, and its thickness is preferably not less than 0.1 μm and not more than 2 μm. In addition, the trench gate electrode TGE (gate trench CH) extending from the main surface S1 of the semiconductor substrate SUB in the vertical direction of the figure reaches at least n - The drift region NDR is preferably formed to reach the insulating layer OX.

[0121] By using SOI in the semiconductor substrate SUB, the LDMOS transistor part passes through the insulating layer OX from p - The substr...

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Abstract

In a semiconductor device, a p+ back gate region (PBG) is set between a first part and a second part (P1, P2) of an n+ source electrode region (SR) on a main surface (S1) and is set on an n+ drain electrode region (DR) side relative to the n+ source electrode region (SR). Thus the semiconductor device with a high conductive voltage resistance can be obtained.

Description

technical field [0001] The present invention relates to semiconductor devices. Background technique [0002] Conventionally, a high breakdown voltage LDMOS (Laterally Diffused Metal Oxide Semiconductor: Laterally Diffused Metal Oxide Semiconductor) has been used. For example, a paper "Theory of Semiconductor Superjunction Devices" (Non-Patent Document 1) discloses a high withstand voltage LDMOS having a trench gate structure. This high withstand voltage LDMOS has a so-called double reduced surface field (Double Resurf: Double Reduced surface filed) structure. [0003] In addition, Japanese Patent Application Laid-Open No. 11-307763 (Patent Document 1) discloses a high withstand voltage MOSFET (Metal Oxide Semiconductor Field Effect Transistor: Metal Oxide Semiconductor Field Effect Transistor) having a back gate region structure. . In this high withstand voltage MOSFET, the source region is disposed so as to face the drain region with the gate electrode interposed therebe...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/78H01L29/08H01L29/06
CPCH01L29/4236H01L29/063H01L29/0653H01L29/1095H01L29/7393H01L29/7825H01L29/0692H01L29/0878H01L29/7835H01L29/0634H01L29/7824H01L29/7813H01L29/7816
Inventor 吉田浩介新田哲也酒井敦
Owner RENESAS ELECTRONICS CORP