FPGA (field programmable gate array) based division operation method and FPGA based division operation device

Abstract

The invention discloses an FPGA (field programmable gate array) based division operation method and an FPGA based division operation device, aiming to reduce resource consumption and widen the numerical calculation range of division operation. The FPGA based division operation method includes acquiring a first data item serving as a divisor in the division operation; judging whether or not the first data item is identical to a prestored data item in a storage list including set data item reciprocals; if yes, directly calling the reciprocal of the data item, identical to the first data item, in the storage list to acquire the reciprocal of the first data item; if not, performing shift operation on the first data item to acquire a second data item capable of being found in the storage list, and determining the reciprocal of the first data item according to the second data item; multiplying the reciprocal of the first data item by a data item serving as a dividend in the division operation to complete the division operation. By the FPGA based division operation method and the FPGA based division operation device, resource consumption can be reduced, and the numerical calculation range of the division operation can be widened.

Description

technical field [0001] The invention relates to the technical field of digital signal processing, in particular to a method and device for performing division operations based on FPGA. Background technique [0002] With the maturity of FPGA (Field Programmable Gate Array) technology, the method of using FPGA to realize digital signal processing is more and more widely used. [0003] The interior of FPGA is composed of a large number of gate arrays, which can perform various complex digital signal operations. It can only operate on fixed-point values, and the division operation requires that the divisor must be in the form of an exponential power of 2, that is, the division operation can only be performed on 1 to 2 32 Integers within the range are divided. For other values, the division cannot be completed because they cannot be mapped to the actual physical device. [0004] Generally, the FPGA uses a separate division module, and the division module directly completes the ...

AI Technical Summary

Problems solved by technology

[0005] However, using the method of separately setting the division module, for different application scenarios, different division modules need to be set, that is, the division module needs to be redesigned every time, and more logic resources are occupied

Using Direct Storage 2 32 The reciprocal of the divisor that needs to be calculated generally needs to consume O(2 32 ) level of logic resources, and occupy more logic resources

[0006] When the division operation is implemented in the existing FPGA, it needs to occupy more logic resources, and due to the limitation of hardware resources, the existing method for implementing the division operation in the FPGA has a limited value range for the division operation, such as storing 2 32 The reciprocal of the divisor that needs to be calculated can only achieve 2 32 A numerical division operation, so how to provide a division calculation method with less resource consumption and a large data range needs to be solved urgently

Images