Method and device achieving MIPI LANE signal serial output on basis of FPGA

Abstract

The invention discloses a method and device achieving MIPI LANE signal serial output on the basis of an FPGA. The method comprises the steps that 1, the data LANE transmission rate of MIPI signals is received from an upper layer, and parallel clock signals and IO serial clocks are generated; 2, the IO serial clocks are converted into two ways of IO serial clocks with the same frequency and the phase difference of 90 degrees; 3, RGB video signals are converted into MIPI set package data to be allocated to each MIPI LANE; 4, one way of IO serial clocks are copied to each LANE, serial and parallel conversion is carried out on the MIPI set package data, and a data LANE signal of each LANE is output; 5, by means of the parallel clock signals, parallel and serial conversion operation is carried out on the other way of IO serial clocks; 6, the clock LANE signals and the data LANE signal of each LANE are converted into clock LANE HS signals and an LVDS differential signal of each LANE respectively; 7, the clock LANE HS signals and the LVDS differential signal of each LANE are converted into MIPI clock LANE signals and MIPI data LANE signals to be transmitted to an MIPI module to be displayed.

Description

technical field [0001] The invention relates to the field of display and testing of MIPI liquid crystal modules, in particular to a method and device for serializing and outputting MIPI LANE signals based on FPGA. Background technique [0002] According to the MIPI DSI and DPHY protocols, the MIPI signal uses serial signal mode to send the video data stream to the module through different LANE data lines for display. A clock signal is sent to the module so that the module can demodulate the serial image data through the clock. [0003] The MIPI LANE clock adopts the DDR method, that is, the upper and lower edges of the clock are aligned with the data center, and the two edges of the clock are used on the module side to demodulate the received serial video data signal. [0004] When the video signal is converted into MIPI packet data and distributed to each data LANE, the packet data on each LANE is serialized in the form of 8:1, that is, the byte data is converted into a se...

AI Technical Summary

Problems solved by technology

[0005] At present, the technical solution for implementing MIPI signals through FPGA has the characteristics of stable operation, easy operation, easy implementation, and low cost. The high-speed signal can work stably and reliably.

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