Method and device for mipi LANE signal serialization output based on fpga

Abstract

The invention discloses a method and device for serializing and outputting MIPI LANE signals based on FPGA. The method includes 1) receiving the data LANE transmission rate of MIPI signals from an upper layer, and generating parallel clock signals and IO serialization clocks; 2) Convert the IO serialization clock to two IO serialization clocks with the same frequency and 90° phase difference; 3) Convert the RGB video signal to MIPI packet data and distribute it to each MIPI LANE; 4) Serialize one IO Copy the clock to each LANE, perform serial-to-parallel conversion on the MIPI packet data, and output the data LANE signal of each LANE; 5) perform a parallel-serial conversion operation on another IO serialized clock through the parallel clock signal to form a clock LANE signal ;6) Convert the clock LANE signal and the data LANE signal of each LANE to the clock LANE HS signal and the LVDS differential signal of each LANE respectively; 7) Convert the clock LANE HS signal and the LVDS differential signal of each LANE to MIPI clock The LANE signal and MIPI data LANE signal are transmitted to the MIPI module for display.

Description

technical field [0001] The invention relates to the field of display and testing of MIPI liquid crystal modules, in particular to a method and device for serializing and outputting MIPILANE signals based on FPGA. Background technique [0002] According to the MIPI DSI and DPHY protocols, the MIPI signal uses serial signal mode to send the video data stream to the module through different LANE data lines for display. A clock signal is sent to the module so that the module can demodulate the serial image data through the clock. [0003] The MIPI LANE clock adopts the DDR method, that is, the upper and lower edges of the clock are aligned with the data center, and the two edges of the clock are used on the module side to demodulate the received serial video data signal. [0004] When the video signal is converted into MIPI packet data and distributed to each data LANE, the packet data on each LANE is serialized in the form of 8:1, that is, the byte data is converted into a ser...

AI Technical Summary

Problems solved by technology

[0005] At present, the technical solution for implementing MIPI signals through FPGA has the characteristics of stable operation, easy operation, easy implementation, and low cost. The high-speed signal can work stably and reliably.

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