System and method for accelerating and decelerating packets

A technology of accelerators and reducers, which is applied in the selection device, electrical components, connection management and other directions of multiplexing systems, and can solve problems such as large bandwidth throughput

Active Publication Date: 2015-08-12
HONOR DEVICE CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Photonic switches tend to be challenging at the speed of establishing and disconnecting connections, but demonstrate tremendous bandwidth throughput when the connections are in place

Method used

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  • System and method for accelerating and decelerating packets
  • System and method for accelerating and decelerating packets
  • System and method for accelerating and decelerating packets

Examples

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Embodiment Construction

[0029] It should be understood at the outset that, although an illustrative implementation of one or more embodiments is provided below, the disclosed systems and / or methods may be implemented using any number of techniques, whether currently known or in existence. The invention should in no way be limited to the illustrative implementations, drawings, and techniques illustrated below, including the exemplary designs and implementations illustrated and described herein, but rather be within the scope of the appended claims and their equivalents Modified within the full range of .

[0030] FIG. 1 illustrates a system 140 for routing packet flows, eg, in a data center. System for Routing Packet Streams U.S. Provisional Application Serial No. 61 / 787,847, filed March 15, 2013, entitled "System and Method for Steering Packet Streams" As further discussed in , this application is incorporated herein by reference. Initially, a packet stream from a top-of-rack (TOR) switch 104 in a ...

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Abstract

In one embodiment, a system for accelerating a packet stream includes a first accelerator configured to re-clock the packet stream from a first clock rate to a second clock rate to produce an accelerated packet stream, where the first clock rate is less than the second clock rate, where the packet stream has a first inter-packet gap, where the accelerated packet stream has a second inter-packet gap, and where the second inter-packet gap is greater than the first inter-packet gap. The system also includes a switch coupled to the first accelerator, where the switch is configured to switch the accelerated packet stream at the second clock rate to produce a switched packet stream.

Description

[0001] Related Applications Cross Application [0002] This application claims the prior art of U.S. Patent Application No. 13 / 901,944, filed May 24, 2013, entitled "System and Method for Accelerating and Decelerating Packets." Claiming priority, the content of this earlier application is incorporated herein by reference as if reproduced in its entirety. technical field [0003] The present invention relates to a system and method for communication, and more particularly to a system and method for accelerating and decelerating packets. Background technique [0004] Data centers route large volumes of data. Currently, data centers may have a throughput of 5 to 7 terabytes per second, which is expected to increase substantially in the future. A data center is composed of a huge number of server racks, storage device racks and other racks, all of which are interconnected via a huge centralized packet switching resource. In this resource, packet switches are used to route pac...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04Q11/00
CPCH04Q11/0062H04W76/04H04Q11/0005H04Q2011/0056H04Q2011/0081H04Q2011/0086
Inventor 阿兰·弗兰克·格拉维斯彼得·艾斯伍德·史密斯多米尼克·古德威尔艾瑞克·伯尼尔
Owner HONOR DEVICE CO LTD
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