Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Manufacturing method of vertical double diffused metal oxide semiconductor field effect transistor

An oxide semiconductor and vertical double-diffusion technology, which is applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of VDMOS device electrical parameter changes, waste of manpower and material resources, and VDMOS device drain-source soft breakdown. Achieve the effect of solving the drain-source soft breakdown and avoiding waste

Active Publication Date: 2017-10-20
FOUNDER MICROELECTRONICS INT
View PDF3 Cites 1 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The invention provides a method for manufacturing a vertical double-diffused metal oxide semiconductor field effect transistor, which is used to solve the problem in the prior art that while solving the soft breakdown of the drain source of the VDMOS device, the remaining electrical parameters of the VDMOS device will be relatively large. Large changes, and the return of these electrical parameters to the target value wastes a lot of manpower and material resources

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Manufacturing method of vertical double diffused metal oxide semiconductor field effect transistor
  • Manufacturing method of vertical double diffused metal oxide semiconductor field effect transistor
  • Manufacturing method of vertical double diffused metal oxide semiconductor field effect transistor

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0025] The technical solution of the present invention will be described in further detail below through specific embodiments and accompanying drawings.

[0026] figure 2 A schematic flowchart of an embodiment of a method for manufacturing a vertical double-diffused metal-oxide-semiconductor field effect transistor provided by the present invention. Such as figure 2 As shown, the method may specifically include:

[0027] S201, depositing an insulating layer on the surface of the silicon nitride layer.

[0028] S202, performing reflow treatment on the insulating layer at a set temperature, where the set temperature is lower than a threshold temperature of drain-source soft breakdown.

[0029] refer to figure 1 Those skilled in the art can understand that before step S201, the following steps are also included: sequentially forming an epitaxial layer 12, a gate oxide layer 13, a polysilicon layer 14, a body region 15, a source region 16, and a silicon nitride layer on the ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention provides a method for manufacturing a vertical double-diffusion metal oxide semiconductor field effect transistor. The method includes: depositing an insulating layer on the surface of the silicon nitride layer; performing reflow treatment on the insulating layer at a set temperature, and the set temperature is lower than the threshold temperature of drain-source soft breakdown. In the manufacturing method of the vertical double-diffused metal oxide semiconductor field effect transistor provided by the present invention, the insulating layer is reflowed at a set temperature lower than the threshold temperature of the drain-source soft breakdown, and the source is reduced by reducing the temperature during the reflow process. The distance of lateral diffusion in the region becomes shorter, and the effective channel length of the body region becomes longer, which reduces the risk of the body region depletion layer punching through to the source region under the reverse biased state of the device body region / epitaxial layer drift region junction, and achieves the solution of device leakage. source for soft breakdown purposes. Moreover, the method basically has no influence on the remaining electrical parameters of the device, thereby avoiding waste of manpower and material resources.

Description

technical field [0001] The invention relates to the technical field of manufacturing semiconductor devices, in particular to a method for manufacturing a vertical double-diffused metal oxide semiconductor field effect transistor. Background technique [0002] Vertical Double-diffusion Metal Oxide Semiconductor (VDMOS) combines the advantages of bipolar transistors and Metal Oxide Semiconductor (MOS), and has a nearly infinite The quiescent input impedance and very fast switching time make it an ideal power device for both switching and linear applications. [0003] figure 1 It is a schematic diagram of the structure of a vertical double-diffused metal-oxide-semiconductor field effect transistor, such as figure 1 As shown, it includes: a substrate 11, an epitaxial layer 12 disposed on the surface of the substrate 11, a partially etched gate oxide layer 13 disposed on the surface of the epitaxial layer 12, and a partially etched gate oxide layer disposed on the surface of th...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336H01L21/3105
Inventor 刘竹张立荣
Owner FOUNDER MICROELECTRONICS INT
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products