SDN-based method and system for preventing head-of-line blocking (HOL)

Abstract

The invention relates to the technical field of electronic communication, and specifically to a method for preventing head-of-line blocking (HOL). The SDN-based method for preventing head-of-line blocking is applied to a SDN network comprising a plurality of switches and comprises the steps as follows: step 1, switches sense the state of an output port according to a set sensing method and report an HOL event to a SDN controller when the output port enters a head-of-line blocking state; step 2, the SDN controller calculates a forward path of the HOL event according to the HOL event so as to obtain an entrance switch and a corresponding input port; step 3, the SDN controller issues OF information to the input port; step 4, the input port drops a message causing the HOL event or limits the speed of the message causing the HOL event after receiving the OF information. By adopting an SDN framework, the method provided by the invention directly limits the message at the source so as to prevent the impact and influence to the whole SDN network to achieve the whole network defense for preventing head-of-line blocking.

Description

technical field [0001] The invention relates to the technical field of electronic communication, in particular to a method and system for preventing thread head blocking. Background technique [0002] Head-of-line blocking (HOL) is a phenomenon that occurs in buffered communication network switching. Such as figure 1 As shown, the switch 1 is generally composed of a buffered input port 11 , a switch fabric 13 and buffered output ports 121 , 122 . Head-of-line blocking is prone to occur when packets arriving on the same input port are directed to different output ports. figure 1 Packet 1 first arrives at the buffered input port 11 at a rate of 100% of the line rate, and packet 1 will be forwarded to the buffered output port 121, and then message 2 arrives at the buffered input port 11 at a rate of 20% of the line rate. Because message 1 is blocked, message 2 cannot be correctly forwarded to the buffered output port 122, that is, due to the FIFO (First Input First Output, f...

AI Technical Summary

Problems solved by technology

figure 1 Packet 1 first arrives at the buffered input port 11 at a rate of 100% of the line rate, and packet 1 will be forwarded to the buffered output port 121, and then message 2 arrives at the buffered input port 11 at a rate of 20% of the line rate. Because message 1 is blocked, message 2 cannot be correctly forwarded to the buffered output port 122, that is, due to the FIFO (First Input First Output, first-in-first-out) feature of the input buffer and switch design, the switch architecture Only packets with cache headers can be exchanged in

Images