Memory erasing method and apparatus

A memory and register technology, which is applied in the direction of response to error generation and redundant code error detection, can solve the problems of increasing the time cost of erasing the memory and reducing the service life of the memory, so as to improve the service life, reduce the time cost and save The effect of time overhead

Active Publication Date: 2015-11-25
HEFEI GEYI INTEGRATED CIRCUIT CO LTD +1
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Problems solved by technology

[0003] Usually, before burning the program in the memory, it is necessary to ensure that the storage area in the memory of the program to be burned is empty, then it is necessary to erase the memory before burning the program. However, in practical applications, not all erasing of the memory Deletion is necessary, and there are two obvious disadvantages to erasing the memory directly: (1) increasing the time overhead of erasing the memory; (2) reducing the service life of the memory

Method used

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  • Memory erasing method and apparatus
  • Memory erasing method and apparatus
  • Memory erasing method and apparatus

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Embodiment Construction

[0076] In order to make the above objects, features and advantages of the present invention more comprehensible, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0077] One of the core concepts of the embodiments of the present invention is to divide the entire memory erasing process into two parts: erasure verification and erasure. Specifically, the upper computer downloads a piece of assembly code used to realize the function of verification and erasure verification (full F verification) to the lower computer. When there is a target file that needs to be written to the lower computer, the lower computer can The code starts to perform erasure verification on the target area used to store the target file. When the erasure verification is completed, the upper computer judges whether to erase the target area according to the verification result fed back by the lower computer. Even in the cas...

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Abstract

Embodiments of the invention provide a memory erasing method and apparatus. The method comprises: receiving an erasing check command sent by an upper computer, wherein the erasing check command comprises target file information; determining a target region by using the target file information, wherein the target area comprises target data; checking the target data according to a preset check rule, to obtain a check result; obtaining, by the upper computer, the check result, and determining, by using the check result, whether the target area is to be erased, if yes, generating, by the upper computer, an erasing command; receiving the erasing command sent by the upper computer; and erasing the target area by using the erasing command. The embodiments of the present invention are used to reduce time overheads for erasing the memory and increase a service life of the memory.

Description

technical field [0001] The invention relates to the technical field of memory data processing, in particular to a memory erasing method and a memory erasing device. Background technique [0002] With the rapid development and wide application of various electronic devices and embedded systems, such as computers, personal digital assistants, mobile phones, digital cameras, etc., there is a great need for a device that can be programmed many times, has a large capacity, is fast to read and write, and can be erased. Convenient, simple, less peripheral devices, low-cost memory. [0003] Usually, before burning the program in the memory, it is necessary to ensure that the storage area in the memory of the program to be burned is empty, then it is necessary to erase the memory before burning the program. However, in practical applications, not all erasing of the memory Deletion is necessary, and direct memory erasure has two obvious disadvantages: (1) increasing the time overhead...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/08
Inventor 王翠荣董瀚琳张乐华王景华
Owner HEFEI GEYI INTEGRATED CIRCUIT CO LTD
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