Semiconductor packaging structure and packaging method

Abstract

The invention discloses a semiconductor packaging structure and a packaging method. the packaging structure comprises a substrate, at least one chip located on the substrate and electrically connected with the substrate, a packaging layer for packaging the at least one chip, and a frame fixed on the upper surface of one chip and upper surfaces of the multiple chips, wherein the frame has a smaller thermal expansion coefficient that the packaging layer. Through fixing the frame on the upper surface of the chip, symmetry of the packaging structure can be added. As the frame has a smaller thermal expansion coefficient that the packaging layer, the thermal expansion coefficient of the packaging layer can be effectively reduced as the frame is additionally arranged. Thus, in the case of temperature rise and fall, the packaging layer and the substrate have basically the same expansion volumes. Warping caused by the thermal expansion coefficient difference can be effectively reduced, the chip can be prevented from being broken, and reliability of the packaging structure is improved.

Description

technical field [0001] The present invention relates to the field of semiconductor packaging, in particular to a semiconductor packaging structure and packaging method. Background technique [0002] There are two main traditional packaging technologies, one is flip-chip bonding (that is, Flip-Chip - flip-chip welding chip), the other is wire bonding (Wirebond), respectively, as Figure 1a and Figure 1b shown. [0003] exist Figure 1a In the illustrated flip-chip packaging technology, a plurality of solder balls 104 are implanted between the chip 103 and the substrate 101 , and the underfill 102 is filled to realize the electrical connection between the chip 103 and the substrate 101 . Afterwards, the chip 103 is packaged with the packaging layer 20 . Wherein, the material of the encapsulation layer 20 may be, for example, molding compound (EMC). exist Figure 1b In the wire bonding packaging technology shown, the chip 103 is pasted on the substrate 101 by using the adh...

AI Technical Summary

Problems solved by technology

However, in the above two packaging technologies, due to the difference in coefficient of thermal expansion (CTE) between the material of the packaging layer 20 (for example, EMC) and the substrate material (for example, FR4 or BT) (for example, the thermal expansion coefficient of a certain EMC is 45ppm, while the thermal expansion coefficient of FR4 used for the substrate is 18ppm), which leads to the unequal expansion volume of the packaging layer 2

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