A kind of preparation method of photolithographic alignment mark
A photolithographic alignment and marking technology, which is applied in the manufacture of semiconductor/solid-state devices, electrical components, circuits, etc., can solve the problems such as the decline in the precision of the power semiconductor device manufacturing process, and achieve the effect of improving the yield of the prepared product
Active Publication Date: 2018-09-18
ZHUZHOU CRRC TIMES SEMICON CO LTD
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[0004] The purpose of the present invention is to provide a preparation method of photolithographic alignment marks to solve the technical problem that the photolithographic alignment marks are affected during the manufacturing process of power semiconductor devices, resulting in a decrease in the precision of the subsequent preparation process of power semiconductor devices
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[0031] The implementation of the present invention will be described in detail below in conjunction with the accompanying drawings and examples, so as to fully understand and implement the process of how to apply technical means to solve technical problems and achieve technical effects in the present invention. It should be noted that, as long as there is no conflict, each embodiment and each feature in each embodiment of the present invention can be combined with each other, and the formed technical solutions are all within the protection scope of the present invention.
[0032] An embodiment of the present invention provides a method for preparing a photolithographic alignment mark, such as figure 1 As shown, the method includes the following steps:
[0033] Step S101 , forming a photolithography alignment mark body through a first photolithography process.
[0034] The photolithographic alignment mark is generally fabricated on the silicon substrate 1 or a thin film grown ...
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Abstract
The invention, which belongs to the technical field of the power semiconductor device, discloses a preparation method of a photoetching alignment mark. With the method, a technical problem that the precision of the subsequent preparation process of the power semiconductor is reduced because the photoetching alignment mark is affected during the power semiconductor device manufacturing process can be solved. The preparation method comprises: a photoetching alignment mark body is formed by a first photoetching technology; generating an insulating layer on the photoetching alignment mark body; and the insulating layer is etched by a secondary photoetching technology to form a protection membrane covering the photoetching alignment mark body, thereby obtaining a needed photoetching alignment mark.
Description
technical field [0001] The invention relates to the technical field of power semiconductor devices, in particular to a preparation method of a photolithography alignment mark. Background technique [0002] A complete power semiconductor device can only be produced through repeated steps of oxidation, diffusion, film deposition, photolithography and etching. In the manufacturing process of power semiconductor devices, photolithography is an important process, which replicates the designed pattern on the silicon wafer through the photoresist layer through glue coating and exposure. [0003] Generally, the power semiconductor device pattern is formed on the silicon wafer through the first lithography and etching, and the alignment mark is also formed for subsequent lithography alignment. From the second lithography, each lithography needs to be aligned with the previous layer. allow. Every time a process step is passed, the lithography alignment mark will be affected, such as...
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IPC IPC(8): H01L21/68
CPCH01L21/68H01L21/682
Inventor 陈辉宋里千程银华郭可刘鹏飞岳金亮
Owner ZHUZHOU CRRC TIMES SEMICON CO LTD