Method for many-core circulation partitioning based on multi-version code generation

Abstract

The invention provides a method for many-core circulation partitioning based on multi-version code generation. A many-core processor is composed of control cores and a calculation core array. Each calculation core is provided with a cache, and the cache which each calculation core is provided with serves as an on-chip memory to perform data transmission with a main memory in a memory direct access mode. The method is characterized in that when a compiler performs parallel transformation on many-core circulation, the particle size of circulation partitioning is determined according to the value indicated by the compiler, so that parallel codes of different versions are generated, the compiler performs feedback of use information stored on a chip during running in a code plug-in mounting mode so that the value indicated by the compiler can be correspondingly adjusted according to the use information fed back, and the utilization rate of the on-chip memory is maximized.

Description

technical field [0001] The invention relates to the field of computer technology, in particular to a many-core loop block method based on multi-version code generation. Background technique [0002] For many-core processors with on-chip storage devices, in order to improve computing performance, it is usually necessary to transfer the data required for computing from the main memory to the on-chip storage through DMA (DirectMemoryAccess, memory direct access), which can greatly reduce memory access. Delay. However, because the on-chip storage capacity is very small, only a small amount of data can be loaded, and the unreasonable division of parallel loops will lead to the ineffective use of on-chip storage devices. If the granularity of loop division is too small, it will lead to frequent DMA, and the utilization rate of on-chip storage is not high. If the granularity of loop division is too large, the data required for calculation cannot be put into the on-chip storage dev...

AI Technical Summary

Problems solved by technology

However, because the on-chip storage capacity is very small, only a small amount of data can be loaded, and the unreasonable division of parallel loops will lead to the ineffective use of on-chip storage devices.

If the granularity of loop division is too small, it will lead to frequent DMA, and the utilization rate of on-chip storage is not high. If the granularity of loop division is too large, the data required for calculation cannot be placed in the on-chip storage device, which will seriously affect the acceleration effect.

[0003] On the other hand, for many-core processors with on-chip storage devices, when the compiler uses the computing core array to accelerate the core cycle in parallel, the usual method is to directly access the data on the main memory or follow the default block The granularity divides the loop in parallel and then uses DMA to transfer the data to the on-chip storage before accessing it, neither of which can effectively utilize the on-chip storage

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