Energy analysis attack resistant symmetric algorithm hardware realization structure

Abstract

The invention relates to an energy analysis attack resistant symmetric algorithm hardware realization structure. The structure contains an original S box (S-Box) of a symmetric algorithm, a complementary S box (C-S-Box) of the symmetric algorithm, and a noise circuit for weakening an output transmission delay effect. The S-Box and the C-S-Box are equivalently two mutually compensatory units in WDLL logic, and always same inputs X and opposite outputs serve as inputs of two same register sets. According to the structure, the existence of S-Box and C-S-Box complementarity ensures that the Hamming specific gravity output by the S-Box in each round is the same as the Hamming distance, so that dynamic energy balance is achieved; and meanwhile, the introduction of a random noise source eliminates the transmission delay effect of a combination circuit and achieves the goal of resisting energy analysis attacks.

Description

technical field [0001] The invention belongs to the technical field of information security chip design, and specifically relates to a hardware implementation structure of a symmetric algorithm for resisting energy analysis attacks based on a random noise complementary S-box, which is widely used in highly secure encryption computing equipment. Background technique [0002] With the continuous popularization of the network and the increasing degree of social informatization, the importance of information security has gradually become prominent. As one of the most powerful weapons in information security, encryption is playing an important role. The symmetric algorithm based encryption is fast, easy to implement, and has gone through a long-term test. [0003] Any security product or cryptographic system must face a problem of how to defend against attacks and snooping. In recent years, a new powerful attack method has emerged, which is called Side Channel Attack (SCA). Sid...

AI Technical Summary

Problems solved by technology

However, there are many difficulties in the design of WDDL circuits, so that WDDL is only theoretical and has not been applied to mass production of chips on a large scale.

With WDDL circuits, the rear-end layout and routing must be done manually, which will consume a lot of time and energy

Without the support of mature EDA software, it is an important reason why WDDL circuits cannot be mass-produced

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