An AES Symmetrical Complementary Hardware Implementation Method Against Energy Analysis Attack

Abstract

An AES symmetric complementary hardware implementation method for resisting power analysis attack comprises the steps that an initial value which is fully complementary with AES initial input logic is set; an initial value which is fully complementary with AES each-round sub-key logic is set; Addkey operation is performed; Subbyte operation is performed; Shiftrow operation is peformed; Mixcolumn operation is performed. According to the method, it is guaranteed that intermediate variable Hamming proportions of each round are equal, and it is guaranteed that the intermediate variable Hamming distance between any two rounds is always zero; The method, for resisting the power analysis attack, implemented on the basis of the RTL level is convenient to implement, complementary logic gate logic does not need to be customized, no influence is exerted on the wiring layout of a backend, and no consideration needs to be given to the physical problems of load balancing, wire interconnection and the like.

Description

technical field [0001] The invention belongs to the technical field of information security chip design, and specifically relates to an AES symmetrical complementary hardware implementation method for resisting energy analysis attacks, which is widely used in highly secure encryption computing equipment. Background technique [0002] With the continuous popularization of the network and the increasing degree of social informatization, the importance of information security has gradually become prominent. As one of the most powerful weapons in information security, encryption is playing an important role. The Advanced Encryption Standard (hereinafter abbreviated as AES) encryption algorithm has experienced a long-term test since it became an advanced encryption standard until today. [0003] Any security product or cryptographic system must face a problem of how to defend against attacks and snooping. In recent years, a new powerful attack method has emerged, which is called...

AI Technical Summary

Problems solved by technology

However, there are many difficulties in the design of WDDL circuits, so that WDDL is only theoretical and has not been applied to mass production of chips on a large scale.

With WDDL circuits, the rear-end layout and routing must be done manually, which will consume a lot of time and energy

Without the support of mature EDA software, it is an important reason why WDDL circuits cannot be mass-produced

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