Copy-on-write circuit applicable to static random access memory
A static random, write-copy technology, applied in the direction of static memory, digital memory information, information storage, etc., can solve the problem of inaccuracy and achieve the effect of reducing the self-timing time of the word line
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[0022] The present invention will be further described in detail below in conjunction with specific embodiments, which are explanations of the present invention rather than limitations.
[0023] like figure 1 Shown, a typical data path instance of SRAM. The data path includes precharge circuits, memory cells, sense amplifiers and write drivers.
[0024] The precharge circuit is composed of PMOS transistors 12,13,15. The storage unit is composed of a pair of cross-coupled inverters 16, 17 and NMOS transmission transistors 19, 20 respectively connected to storage nodes 22, 23. Sensitive amplifiers such as figure 1 Sensitive amplifier 36 in the middle. The write driver consists of an inverter 38 and a pair of tri-state inverters 35,37.
[0025] In the hold mode of the SRAM, the word line 14 of the memory cell is inactive (active high), and the bit line 18 and bit line 21 are kept at the precharge level VDD. Since the NMOS transmission transistors 19 and 20 are turned off ...
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