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Copy-on-write circuit applicable to static random access memory

A static random, write-copy technology, applied in the direction of static memory, digital memory information, information storage, etc., can solve the problem of inaccuracy and achieve the effect of reducing the self-timing time of the word line

Active Publication Date: 2016-06-15
XI AN UNIIC SEMICON CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The write copy unit 300 only simulates the word line during the normal write operation, and does not simulate the bit line and the write driver during the normal write operation, and the write operation is a single-ended write operation, so it is not accurate enough

Method used

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  • Copy-on-write circuit applicable to static random access memory
  • Copy-on-write circuit applicable to static random access memory
  • Copy-on-write circuit applicable to static random access memory

Examples

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Embodiment Construction

[0022] The present invention will be further described in detail below in conjunction with specific embodiments, which are explanations of the present invention rather than limitations.

[0023] like figure 1 Shown, a typical data path instance of SRAM. The data path includes precharge circuits, memory cells, sense amplifiers and write drivers.

[0024] The precharge circuit is composed of PMOS transistors 12,13,15. The storage unit is composed of a pair of cross-coupled inverters 16, 17 and NMOS transmission transistors 19, 20 respectively connected to storage nodes 22, 23. Sensitive amplifiers such as figure 1 Sensitive amplifier 36 in the middle. The write driver consists of an inverter 38 and a pair of tri-state inverters 35,37.

[0025] In the hold mode of the SRAM, the word line 14 of the memory cell is inactive (active high), and the bit line 18 and bit line 21 are kept at the precharge level VDD. Since the NMOS transmission transistors 19 and 20 are turned off ...

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PUM

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Abstract

The invention relates to a copy-on-write circuit applicable to a static random access memory. The copy-on-write circuit comprises a row decoder, a storage array, a copy bit line load, a control circuit and pre-decoder, a copy word line load, a copy-on-write unit, a sensitive amplifier and write drive, a copy-on-write drive and a state machine; the row decoder is connected with the storage array and the copy bit line load by virtue of a plurality of word lines; the storage array is connected with the copy word line load, the sensitive amplifier and the write drive by virtue of a plurality of bit lines; the copy bit line load is connected with the copy-on-write unit and the copy-on-write drive; the control circuit and pre-decoder is connected with the state machine and the copy-on-write drive by virtue of a write starting signal; the output end of the control circuit and pre-decoder is connected with an address and write enable / clock; the copy word line load is connected with the state machine, the copy-on-write unit and the copy-on-write drive by virtue of the copy word line; the copy-on-write unit is connected with the state machine; the sensitive amplifier and write drive is connected with a write data signal and a read data signal; and the state machine is connected with the row decoder.

Description

technical field [0001] The invention relates to the field of static random access memory design, in particular to a write copy circuit suitable for static random access memory. Background technique [0002] As an important storage element in integrated circuits, SRAM is widely used in high-performance computer systems (CPU), system-on-chip (SOC), handheld devices, etc. due to its high performance, high reliability, and low power consumption. computing field. [0003] With the continuous evolution of process technology and the continuous shrinking of the size of semiconductor devices, local and global process deviations have an increasing impact on the performance and reliability of integrated circuits. In order to overcome this effect, some on-chip adaptive technologies that are not sensitive to process voltage temperature (PVT) have been widely researched and applied in recent years. By adding a copy circuit on the chip, to track the impact of PVT environmental changes on...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C11/419
CPCG11C11/419
Inventor 熊保玉
Owner XI AN UNIIC SEMICON CO LTD
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