22 results about "Process voltage temperature" patented technology

The invention relates to the technical field of chip delay error dynamic compensation scheme design, in particular to a chip delay error dynamic compensation method and system based on TDC. The method comprises the following steps: measuring the transmission delay of a critical path in real time by using a time-to-digital converter core integrated in a chip; dynamically predicting a future delay error through an embedded algorithm based on the delay measurement value; and according to the predicted delay error, dynamic compensation is carried out on the chip timing sequence, and the compensation comprises adjustment of a clock signal or modification of path delay. A corresponding system includes a TDC core for real-time measurement, an embedded processing unit for running a predictive algorithm, and a dynamic compensation unit for performing compensation. Closed-loop control is formed through real-time monitoring, prediction and compensation, the influence of process, voltage and temperature changes on the time sequence of the chip can be effectively resisted, the time sequence precision, working stability and reliability of the chip are remarkably improved, and the method is particularly suitable for high-frequency and precise measurement chips.

A unified timing closure system for the simultaneous synthesis of multi-mode clock trees in a system-on-chip architecture, comprising: a timing convergence processor configured to perform simultaneous analysis and optimization of clock distribution paths across a variety of operating modes and process voltage-temperature operating conditions, wherein the timing convergence processor maintains a unified timing graph that correlates all clock sinks with multiple mode vectors representing setup and hold relationships under different conditions; a multitude of distributed computer scaling units distributed across physically distinct sub-areas of the system-on-chip architecture, each distributed computer scaling unit being configured to determine local delay scaling factors corresponding to process variations, voltage fluctuations, and temperature gradients in its respective sub-area, and dynamically adjust the delay buffer characteristics, link impedance, and driver strength in response to the local scaling factors; a clock offset synchronization unit coupled with the timing convergence processor and the numerous distributed clock scaling units, wherein the clock offset synchronization unit is configured to monitor and minimize insertion delay differences between multiple clock sinks by dynamically adjusting capacitive loads and buffer driver strengths throughout the clock network to maintain uniform propagation characteristics across all modes; a multi-mode synchronization processor that is operationally linked to the timing convergence processor and is configured to harmonize clock arrival times across the operating modes of function, test, and power saving by mapping all mode-specific constraints into a unified timing domain, and to correct inter-mode skew divergence by iteratively adjusting clock path latencies; a distributed timing communication interface that establishes a hierarchical interconnection network between the timing convergence processor and the multiple distributed corner scaling units, wherein the distributed timing communication interface is configured to exchange real-time timing information, delay deviation metrics, and control instructions via a synchronized token-based communication protocol; and A physical time-matching circuit consisting of tunable delay lines, programmable capacitive elements and temperature-compensated bias transistors, physically embedded in the clock distribution network, wherein the physical time-matching circuit receives adaptive control signals from the time convergence processor and adjusts local propagation characteristics to achieve time completion simultaneously across all operating modes and process boundaries.

The application discloses a nano-ampere current source with process voltage temperature compensation capability and a design method, comprising a current bias circuit and an adaptive constant current bias voltage generating circuit; the current bias circuit is used for realizing nano-ampere sub-threshold current bias; the bias voltage generating circuit is used for extracting the characteristics of a target circuit under different processes, power supply voltages and temperature conditions, so as to obtain a corresponding bias voltage variation characteristic curve and guide the construction of the current bias circuit. The nano-ampere current source with process voltage temperature compensation capability can not only provide accurate current bias for a sub-threshold circuit, but also has the ability to resist process, power supply voltage and temperature fluctuations, and can avoid the use of large-size current mirror MOS tubes, thereby saving the layout area.

The apparatus includes: a ring oscillator including a set of cascaded current-starved inverters arranged in a ring; a set of field effect transistors (FETs) coupled in series with the set of cascaded current-starved inverters between an upper voltage rail and a lower voltage rail, respectively; a negative to absolute temperature (NTAT) current source configured to generate a NTAT current; and one or more current mirrors coupling the NTAT current source to the set of FETs.

The invention discloses a pulse width detection circuit and a field programmable gate array, and belongs to the technical field of integrated circuits, the circuit comprises a time delay module, a serial-to-parallel conversion module and a control module, at least one of the time delay module and the serial-to-parallel conversion module is circuit-cured; the first input end of the time delay module is used for receiving a periodic first signal, the second input end of the time delay module is connected with the output end of the control module and used for receiving the control quantity output by the control module, and the output end of the time delay module is connected with the first input end of the serial-parallel conversion module and used for outputting a second signal; the output end of the serial-parallel conversion module is connected with the first input end of the control module and used for outputting first data, and the control module is used for determining the pulse width of the first signal based on the first data corresponding to the multiple different control quantities. The circuit can be simplified, resource occupation is reduced, cost is reduced, and interference from technology, voltage, temperature and power supply noise is small.

The apparatus includes: a ring oscillator including a set of cascaded current-starved inverters arranged in a ring; a set of field effect transistors (FETs) coupled in series with the set of cascaded current-starved inverters between an upper voltage rail and a lower voltage rail, respectively; a negative to absolute temperature (NTAT) current source configured to generate a NTAT current; and one or more current mirrors coupling the NTAT current source to the set of FETs.

The invention relates to a voltage-controlled oscillator, and the oscillator comprises a first control unit which outputs a first current based on a control voltage; the second control unit outputs second current based on the control voltage, the second control unit further comprises a switch module, and the switch module is used for controlling on-off of the second control unit; and the oscillation circuit is connected to the first control unit and the second control unit, and changes the gain of the voltage-controlled oscillator based on the adjustment of the switch module of the second control unit. According to the voltage-controlled oscillator provided by the invention, by additionally arranging the control unit, the coverage of the target frequency under the change of the process, the voltage and the temperature is ensured, and the function and the performance of the voltage-controlled oscillator are hardly influenced when the additionally arranged control unit does not work.

A threshold-adjustable inverter circuit with self-adaptive substrate bias comprises an operational amplifier, a main inverter, a replica inverter and a substrate bias generation circuit, the main inverter, the replica inverter and the substrate bias generation circuit are connected with the operational amplifier, and the positive input end of the operational amplifier is connected with the replica inverter with input and output short circuit. The output end of the operational amplifier is connected with the substrate bias generation circuit through the bias resistor and further connected to the substrate bias voltage ends of the main phase inverter and the replica phase inverter, and the input end and the output end of the main phase inverter serve as the input end and the output end of the adjustable threshold phase inverter circuit; the operational amplifier compares threshold voltage output by the replica inverter with external set voltage and outputs a control signal to the substrate bias generation circuit, substrate bias voltage of the main inverter and the replica inverter is generated, the replica inverter threshold value is locked to the external set voltage through a negative feedback mechanism, the bias voltage is applied to the main inverter, and the main inverter and the replica inverter are connected. And self-adaptive adjustment of the threshold value is realized. Closed-loop negative feedback is formed by copying the phase inverter and the operational amplifier, real-time tracking and calibration of the threshold voltage are achieved, accurate control over the threshold voltage of the phase inverter is actively achieved by adjusting the substrate voltage, and the threshold value is kept stable under changes of the technology, the voltage and the temperature. The circuit is suitable for a low-power-consumption and high-stability digital circuit and analog mixed signal system, can replace the traditional fixed threshold design, and improves the robustness of the system.

The application relates to the technical field of low-power consumption of integrated circuits, and discloses a RAM (Random Access Memory) voltage maintaining circuit and method in a sleep mode, which comprises a reference current generating module, a current mirror array module, a core voltage generating module and a digital calibration control module; the reference current generating module generates nanampere reference current; the current mirror array module outputs programmable mirror current; the core voltage generating module converts the mirror current into output voltage VOUT; and the digital calibration control module compares Vto with Vref when the chip is working, and outputs a calibration signal to adjust the mirror current. The core voltage generating module comprises a PVT self-adaptive bias structure composed of NMOS and PMOS tubes, so that the output voltage is automatically adjusted according to process, voltage and temperature. The application adopts an intermittent working mode of "calibration during working and maintaining during sleeping", and combines an open-loop source follower architecture, so that typical static power consumption of 50nA, PVT self-adaptive adjustment, rapid awakening and extremely small chip area are realized, and the application can be widely applied to super-low-power-consumption devices such as the Internet of Things.

The application discloses a memory computing circuit, comprising a computing component array and an analog-to-digital conversion circuit, the computing component array is used for analog computing operation, the computing component array comprises a memory unit, a first group of computing components and a second group of computing components, the first group of computing components provides capacitance for the analog computing operation in response to an input vector and receives data from a plurality of memory units and the input vector, the second group of computing components provides capacitance for quantization, each computing component of the computing component array is based on a switched capacitor circuit, the analog-to-digital conversion circuit comprises a comparator and a conversion control unit, the comparator has a signal end, a reference end and a comparison output end, wherein the first and second groups of computing components are selectively coupled to the signal end and the reference end. The memory computing circuit of the application can effectively reduce errors and can reduce or avoid inaccuracy caused by process / voltage / temperature (PVT) drift.

The invention discloses a ring amplifier circuit adopting a replica bias and bias enhancement technology. The ring amplifier circuit comprises a first amplification stage, a second amplification stage, a third amplification stage, a replica bias loop and an output stage bias enhancement circuit, in the replica bias loop, the circuit structure of a replica branch is the same as that of the second amplification stage, and the circuit parameter of the replica branch is in 1 / N proportion to that of the second amplification stage; the output stage bias enhancement circuit comprises a second amplification stage bias resistor connected in series between the PMOS transistor and the NMOS transistor of the second amplification stage A2, and a cross connection mode from the output of the second amplification stage to the input of the third amplification stage; the cross connection mode is that the high output node voltage of the second amplification stage is connected to the NMOS transistor input of the third amplification stage, and the low output node voltage of the second amplification stage is connected to the PMOS transistor input of the third amplification stage. By designing a replica bias loop and an output stage bias enhancement technology, comprehensive balance between stable performance and high-speed and high-precision performance requirements under different process, voltage and temperature conditions is realized.

The invention relates to the technical field of analog integrated circuits, in particular to a high-bandwidth isolation current detection amplifier circuit, a current detection method and a current detection chip. The current detection amplifier circuit comprises a high-voltage side circuit and a low-voltage side circuit which are electrically isolated; in the high-voltage side circuit and the low-voltage side circuit, a to-be-measured voltage is converted into a differential amplification voltage signal through a fully-differential differential amplifier; a feedback loop of a cross-isolation transmission path is formed by a first clamping amplifier, a first voltage-controlled oscillator, a second frequency voltage converter, a second voltage follower, a second voltage-controlled oscillator, a second clamping amplifier, a third frequency voltage converter and a first frequency voltage converter, so that a large bandwidth is provided; under the condition of process-voltage-temperature change, high current detection precision and accuracy are ensured, and influence caused by different processes, temperatures and the like of the high-voltage side circuit and the low-voltage side circuit is avoided.

This invention discloses a pseudo-resistor circuit, an RC filter circuit, a current mirror circuit, and a chip. The pseudo-resistor circuit includes a first MOSFET and a bias circuit. The bias circuit provides a bias voltage between the gate and source of the first MOSFET to enable the first MOSFET to operate in the subthreshold region, and adjusts the resistance value of the first MOSFET by adjusting this bias voltage. The pseudo-resistor circuit, RC filter circuit, current mirror circuit, and chip of this invention can achieve a high resistance value with a smaller area. This reduces the resistor area and allows for a smaller capacitor value to achieve the same RC time constant, thus reducing the capacitor area. Furthermore, the resistance value of this pseudo-resistor is less affected by process voltage-temperature (PVT), ensuring that the filtering effect of the RC filter does not change significantly with variations in PVT.

The invention belongs to the field of electric energy conversion, and discloses a zero-crossing current detection circuit robust to PVT change and application of the zero-crossing current detection circuit, and a ZCD circuit comprises a current signal detection unit, a current signal equal-ratio amplification unit, a current signal reconstruction unit and a reference voltage generation unit. Compared with the traditional zero-crossing current detection technology, the detection technology realizes the accurate detection of the zero-crossing current through the equal-ratio amplification of the current signal. The detection technology can be widely applied to any switch inductance converter circuit, and has extremely high robustness to PVT (process, voltage and temperature) changes. And meanwhile, when the technology is used, no extra current sampling resistor is introduced into the circuit, so that the influence on the overall efficiency is small.

This invention discloses a post-processing circuit for writing true random numbers in sub-nanosecond mode using a voltage-controlled magnetic anisotropic magnetic tunnel junction (VCMA-MTJ). The circuit includes an entropy source for a 2-transistor, 2-MTJ magnetic random access memory array, a dual-channel single-ended readout circuit, a latch circuit, a cascaded XOR circuit, and a timing control circuit. The 2T2M array acts as the physical entropy source, outputting raw random signals through two independent VCMA-MTJ channels. The readout circuit converts the impedance differences of the VCMA-MTJs into digital signals, ensuring the independence of the two signals. The latch circuit temporarily stores the initial read signal, and the cascaded XOR circuit performs an XOR operation with the second read signal to output high-quality random numbers. The timing control circuit coordinates the orderly operation of each module through asynchronous signals REN, WEN, and EN. The word line WL is a sub-nanosecond narrow pulse signal, and WEN indicates the write timing; the two work together to achieve high-speed sub-nanosecond writing. This circuit effectively resists random number deviations caused by device non-ideals and PVT (process-voltage-temperature) fluctuations, improving circuit integration.

This invention relates to a CDAC and comparator co-circuit based on dynamic power consumption optimization, belonging to the field of analog integrated circuit technology. Addressing the technical problem of excessive power consumption in existing SARADCs for medium- and high-speed applications, this invention achieves a balance between low power consumption and high performance through innovative design of the core modules. Its core architecture includes a clock generation circuit, input buffer, reference voltage circuit, sample-and-hold circuit, differential CDAC circuit, comparator, SAR logic circuit, and output latch circuit. The focus is on low-power optimization of the comparator, input buffer, CDAC circuit, and SAR logic circuit. This invention achieves a sampling rate of 48MS / s and a resolution of 10 bits under 22nm process and 0.8V power supply voltage, effectively reducing the power consumption of key modules and improving the circuit's adaptability to process, voltage, and temperature (PVT) fluctuations. It can be widely applied to power-sensitive electronic devices such as portable medical devices, IoT sensors, and high-speed data acquisition systems.

The present disclosure relates to a system-on-chip including a PVT sensor and a corresponding PVT sensing method. A system-on-chip includes a process voltage temperature (PVT) sensor having a filter circuit that initiates a patterned digital signal and propagates the patterned digital signal in a manner responsive to changes in a semiconductor material of the system-on-chip, an operating power supply voltage, and an operating temperature. A digital comparison circuit compares the initiated patterned digital signal and the propagated patterned digital signal. In response to detecting a comparison of a difference between the initiated patterned digital signal and the propagated patterned digital signal, a warning signal is generated.

The invention relates to the technical field of integrated circuit low power consumption, and discloses an RAM holding voltage generation circuit and method in a sleep mode, and the circuit comprises a reference current generation module which generates a nanoampere-level reference current; the current mirror image array module is used for outputting a programmable adjustable mirror image current; the core voltage generation module is used for converting the mirror current into output voltage VOUT; and the digital calibration control module is used for comparing the Vto with the Vref when the chip works, and outputting a calibration signal to adjust the mirror current. The core voltage generation module comprises mutually overlapped PVT adaptive bias structures composed of NMOS and PMOS transistors, so that the output voltage is automatically adjusted along with the process, the voltage and the temperature. According to the invention, an intermittent working mode of calibrating during working and keeping during sleeping is adopted, and an open-loop source follower architecture is combined, so that static power consumption with a typical value of 50nA, PVT self-adaptive adjustment, rapid wakeup and extremely small chip area are realized, and the circuit can be widely applied to ultra-low power consumption equipment such as the Internet of Things and the like.

A system includes a low power, low phase-noise Inductance Capacitance voltage controlled oscillator (LC-VCO), a LC-VCO supply regulator configured to regulate a power supply to the LC-VCO, and a feedback network connected to the LC-VCO supply regulator. The feedback network is configured to track a process voltage temperature (PVT) variation of metal-oxide-semiconductor field-effect transistors (MOSFETs) used in a negative transconductance circuit of the LC-VCO, and to regulate a loop gain of the LC-VCO across PVT variation. The feedback network includes a first MOSFET, wherein the first MOSFET is configured to act as a switch, a first resistor connected across the first MOSFET, a current source device biased with a bandgap voltage, a diode and current-mirror pair, the diode and current-mirror pair including a second MOSFET and a third MOSFET, and a constant current source connected to the current source device and the diode and current-mirror pair.

This invention discloses a hysteresis control circuit based on a multiphase power supply. The hysteresis control circuit includes multiple DC-DC converter units connected in parallel. The output of the hysteresis comparator module is connected to the DC-DC converter via a frequency control module. The frequency control module compares the switching frequency of the switching control signal output by the hysteresis comparator module with a reference switching frequency. When the switching frequency is greater than the reference switching frequency, the frequency control module sends a first adjustment command to the control terminal of the hysteresis comparator module to increase the width of the hysteresis window of the hysteresis comparator module, thereby reducing the actual switching frequency of the switching control signal finally output by the hysteresis comparator module to the DC-DC converter. In this way, by adjusting the switching frequency of the switching control signal output by the hysteresis comparator module in real time through the frequency control module, it is ensured that each DC-DC converter unit can accurately stabilize its switching frequency at the set value when conditions such as process, voltage, and temperature change, thus improving the stability of the circuit.

A system includes a low power, low phase-noise Inductance Capacitance voltage controlled oscillator (LC-VCO), a LC-VCO supply regulator configured to regulate a power supply to the LC-VCO, and a feedback network connected to the LC-VCO supply regulator. The feedback network is configured to track a process voltage temperature (PVT) variation of metal-oxide-semiconductor field-effect transistors (MOSFETs) used in a negative transconductance circuit of the LC-VCO, and to regulate a loop gain of the LC-VCO across PVT variation. The feedback network includes a first MOSFET, wherein the first MOSFET is configured to act as a switch, a first resistor connected across the first MOSFET, a current source device biased with a bandgap voltage, a diode and current-mirror pair, the diode and current-mirror pair including a second MOSFET and a third MOSFET, and a constant current source connected to the current source device and the diode and current-mirror pair.

The application provides a spread spectrum clock generator and an electronic device, the spread spectrum clock generator adds a second loop on the basis of a traditional clock generator loop (i.e. a first loop), the second loop draws a corresponding voltage from a loop filter in the traditional clock generator loop, and generates a corresponding second voltage to control the modulation frequency and modulation depth of the spread spectrum of the output of a ring oscillator in the traditional clock generator loop, the scheme is simple and easy to implement, can effectively improve the electromagnetic interference (EMI) problem, and can avoid using a sigma-delta modulator, greatly reduces the clock jitter of the output of the first loop, improves the reliability, and is suitable for the application requirements of a spread spectrum phase-locked loop. Further, the second loop is implemented by using a pure analog circuit, and has a simple structure, a small area and low cost. In addition, by adjusting the parameters in the second loop, the modulation frequency and modulation depth of the spread spectrum can be changed with process, voltage and temperature (PVT).