Adaptive read wordline voltage boosting apparatus and method for multi-port SRAM

Abstract

Embodiments of the invention are directed to systems and methods for adaptively boosting the supply voltage to an SRAM (104) in response to process-voltage-temperature variations when needed. Embodiments include a critical path (114) that simulates a typical memory cell (104) and read-out circuit (102) in the SRAM. An indication of when to boost the supply voltage to the read-out circuits of the SRAM is provided by applying a trigger signal to a word-line input port (123) of the critical path and comparing the output (125) of the critical path with a reference-latch signal (127).

Description

[0001] Claim of priority under 35 U.S.C. §119 [0002] The title of this patent application filed on September 12, 2011 is "Apparatus for adaptive read word-line boosting within a multi-port SRAM (APPARATUS FOR ADAPTIVE READ WORD-LINE BOOSTING WITHIN A MULTI-PORT SRAM) 61 / 533,647, which is assigned to the assignee of the present case and is hereby expressly incorporated herein by reference. technical field [0003] This invention relates to electronic circuits and, more particularly, to static random access memories. Background technique [0004] Static Random Access Memory (SRAM) is a common type for its non-volatility, low power dissipation, and suitability for high-speed operation. [0005] An example of an SRAM memory cell is illustrated in Figure 5 middle. It is a so-called eight-transistor (8T) SRAM cell, where the eight transistors in the cell are labeled M1 through M8. exist Figure 5 In , the write word line is denoted WWL, the write bit line and its compleme...

AI Technical Summary

Problems solved by technology

For example, the cell read current of weak bits may affect and degrade the performance of SRAM cache memory

Also, weak bits have higher voltage sensitivity due to higher threshold voltages, which can lead to worse performance degradation than performance degradation due to supply voltage noise

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