5 results about "Voltage noise" patented technology

The present application relates to the field of integrated circuits and photoelectric detection technology, in particular to a low-noise hybrid domain CMOS detector readout circuit.The circuit includes a capacitance feedback transimpedance amplification unit, a switched capacitor reference unit, an analog domain readout unit, a time domain quantization unit and an output selection unit.The transimpedance amplification unit converts the pixel current into voltage.The switched capacitor reference unit filters out the reference voltage noise in the reset stage and maintains the reference potential in the integration stage.The analog domain readout unit outputs analog voltage, and the time domain quantization unit outputs digital time code through saturation time detection.The output selection unit defaults to output analog signal, and switches to digital output when the transimpedance amplifier output voltage reaches the preset threshold.The present application also provides a corresponding readout method.The present application can effectively filter out the reference voltage source noise and power supply ripple, significantly improve the signal-to-noise ratio of micro-light detection, realize high dynamic range in a single frame, significantly expand the linear response range of the detector, and can be integrated on chip.

Systems and methods are disclosed that monitor for supply noise from a power source using a voltage noise monitor (VNM). For instance, the VNM may include voltage sense circuitry comprising a controllable resistor that is controlled using threshold information. The resistance of the controllable resistor may be changed based on closing and / or opening one or more switches associated with step resistors using the bits from the threshold information. Furthermore, the VNM may include digital circuitry that comprises a hold finite state machine and a sticky hold counter. Using the digital circuitry, the VNM may be configured to hold a noise detection event for a plurality of clock cycles. In addition, the VNM may perform a calibration process based on setting two voltages for the power source to obtain two codes, and determining a transfer function based on the two voltages and the two codes.

The application discloses a method and device for arranging attenuators in a read input link and a storage medium, comprising: determining a total attenuation value required by the read input link according to a first thermal noise photon number of a read signal transmitted from a room temperature environment to a read cavity of a quantum chip along the read input link and a second thermal noise photon number of the read cavity when normally working; arranging at least one attenuator in a higher temperature zone and a lowest temperature zone of a refrigerator according to the total attenuation value; determining a total voltage noise power spectral density of all temperature zones according to attenuation values, numbers and temperature zones of the attenuators; determining an equivalent temperature of the read cavity according to the total voltage noise power spectral density; and judging whether the equivalent temperature is lower than a threshold value, if yes, the arrangement of the attenuators is reasonable, and if not, adjusting the number and / or attenuation value of the attenuators until the equivalent temperature is lower than the threshold value. The method can accurately select an arrangement of the attenuators whose thermal noise meets the normal working of the quantum chip.

The application discloses a logic circuit and method for improving power conversion product up and down power operation stability, which comprises an up power shielding protection circuit, a de-bounce processing circuit, a protection logic execution circuit, a down power self-help discharge circuit and a protection execution device; the up power shielding protection circuit is used for shielding a false protection signal in a product up power process; the de-bounce processing circuit is used for shielding voltage noise and burr in a starting up power and normal protection logic process; the protection logic execution circuit is used for generating a signal for executing protection logic; the down power self-help discharge circuit is used for timely discharging charges stored in a capacitor of the up power shielding protection circuit in a product down power process; and the protection execution device is used for executing a logic protection action. The application can effectively solve product working stability and fault tolerance problems.

The application provides a noise measurement method and a noise measurement system, wherein the noise measurement method comprises the following steps: presetting n groups of read-out voltage signals to be read out with different amplitudes in an open-loop mode, adjusting the size of the bias current signal of an n-time direct-current superconducting quantum interference device, and obtaining corresponding read-out voltage signals; reading out the voltage noise corresponding to the n-time bias current signal in the previous step in a closed-loop locking mode, and recording the voltage noise as n groups of voltage noise signals; converting each voltage noise signal to obtain corresponding magnetic flux noise signals, and performing a preset fitting algorithm to obtain the device magnetic flux noise of the direct-current superconducting quantum interference device and the introduced noise of the magnetic flux locking read-out circuit. The application distinguishes the device magnetic flux noise of the direct-current superconducting quantum interference device and the introduced noise of the magnetic flux locking read-out circuit through the preset algorithm, thereby avoiding the problem of inaccuracy caused by regarding all the voltage noise as the device magnetic flux noise of the direct-current superconducting quantum interference device.