Semiconductor integrated circuit compensating jitter and jitter compensation method

Abstract

The invention relates to a semiconductor integrated circuit compensating jitter and a jitter compensation method. A data I / O interface for an integrated circuit device includes a noise detector receiving a power supply voltage, detecting a power supply voltage noise component, and providing a clock delay control signal in response to detected power supply voltage noise component. The data I / O interface also includes a clock delay circuit providing a delayed clock signal in response to the clock delay control signal, and a data transfer circuit powered by the power supply voltage and providing output data synchronously with the delayed clock signal.

Description

[0001] Cross References to Related Applications [0002] This US nonprovisional patent application claims priority to the Korean patent application filed on April 8, 2009 under 35 U.S.C § 119, the subject matter of which is incorporated herein by reference. technical field [0003] The inventive concept relates generally to data transfer circuits, integrated circuit devices incorporating data transfer circuits, and methods of controlling the operation of data transfer circuits that compensate for clock signal jitter that occurs in accordance with power supply voltage variations. compensate. Background technique [0004] As integrated circuit devices are increasingly required for greater data bandwidth and increased functionality, the transmission frequency at which data is received by and transmitted from such devices has increased. Increasing the data input / output (I / O) frequency causes many problems because conventional circuits are generally not adapted to operate at suc...

AI Technical Summary

Problems solved by technology

However, the wrong clock edge and uneven clock period of the jittered clock signal lead to multiple erroneous input data (Din) gating operations and output data (Dout) to provide wrong data content

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