Voltage level converter

Abstract

The disclosed voltage-level translator, which comprises a draw-up circuit, a path cutting circuit to separate the draw-up / down circuits when translating, a voltage drop circuit, and a draw-down circuit constructed by thin-grid transistor for the low received voltage to improve switch speed. This invention avoids the competition between draw-up and down circuits, and reduces output voltage noise and jitter.

Description

technical field [0001] The invention relates to a voltage level shifter, in particular to a voltage level shifter capable of reducing noise and jitter phenomena at an output end. Background technique [0002] As far as modern integrated circuit systems are concerned, their core logic units and I / O units usually use two different supply voltages. Taking the 0.13 μm process as an example, the core logic unit is usually supplied with a voltage of 1.2 volts, while the I / O unit is usually supplied with a voltage of 3.3 volts. Due to the different operating voltages, a conversion circuit is required between the core logic unit and the I / O unit to convert the 1.2 volts to 3.3 volts. This conversion circuit is generally called a "voltage level converter". [0003] figure 1 Shown is a conventional voltage level shifter 10, which includes PMOS transistors PG1 and PG2, NMOS transistors NG1 and NG2, and an inverter INV, wherein the PMOS transistors PG1 and PG2 are called pull-up trans...

AI Technical Summary

Problems solved by technology

[0005] In addition, since the highest voltage that the NMOS transistors NG1 and NG2 can withstand is about 2.5 volts, the gate must be made thicker, so the threshold voltage is also higher

At this time, the lower input voltage Vin cannot turn on the NMOS transistors NG1 and NG2, so the switching speed of the NMOS transistors NG1 and NG2 is slow

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