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Method and system for providing smart memory architecture

A memory system and memory technology, applied in static memory, digital memory information, information storage, etc., to achieve efficient operation, reduce power consumption, and reduce I/O load

Active Publication Date: 2013-08-14
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0024] Unfortunately, with STT-RAM or any other type of memory chip, manufacturing or other defects may cause not all memory cells on the memory chip to function properly

Method used

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  • Method and system for providing smart memory architecture
  • Method and system for providing smart memory architecture
  • Method and system for providing smart memory architecture

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Embodiment Construction

[0088] Reference will now be made in detail to embodiments of the inventive concept, examples of which are illustrated in the accompanying drawings. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the inventive concepts. However, it is understood that one of ordinary skill in the art may practice the inventive concept without these specific details. In other instances, well-known methods, procedures, components, circuits, and networks have not been described in detail so as not to unnecessarily obscure aspects of the embodiments.

[0089] It will be understood that, although the terms first, second etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first circuit could be termed a second circuit, and, similarly, a second circuit could also be termed a first circu...

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Abstract

A smart memory system preferably includes a memory including one or more memory chips, and a processor including one or more memory processor chips. The processor includes a common address / data / control memory bus that is configured to provide an asynchronous handshaking interface between the memory array and the memory processor. The processor can offload error data from the memory chip for analysis, and can store poor retention bit address information for memory refreshing in a non-bolatile error retention memory. Porgram logic can also be included for memory address re-configuration. Power management logic can also be included, which can have a process-voltage-temperature compensation voltage generator for providing stable and constant read currents. An asynchronous handshaking interface is provided between the memory array and the memory processor. Write error tagging and write verification circuits can also be included.

Description

[0001] Cross References to Related Applications [0002] This application claims common assignee U.S. Provisional Application No. 61, entitled "A METHOD AND SYSTEM FOR PROVIDING A SMART MEMORY ARCHITECTURE," filed February 11, 2012 / 597,773, and the benefit of U.S. Patent Application Serial No. 13 / 691,639, filed November 30, 2012, the contents of which are hereby incorporated by reference. technical field [0003] The inventive concepts relate to smart memory architectures, and more particularly, to methods and systems for providing smart memory architectures for resistive-type memories. Background technique [0004] The inventive concept relates to memory systems for storing and retrieving information from memory integrated circuits, including static random access memory (SRAM), dynamic random access memory (DRAM), flash memory, phase change random access memory (PCRAM), Spin-transfer torque random access memory (STT-RAM), magnetic random access memory (MRAM), resistive ra...

Claims

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Application Information

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IPC IPC(8): G11C29/56
CPCG11C13/0002
Inventor A.E.昂
Owner SAMSUNG ELECTRONICS CO LTD
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