Adaptive read word line voltage boosting device and method for multi-port SRAM

Abstract

Embodiments of the present invention are directed to systems and methods for adaptively boosting supply voltage to static random access memory SRAM (104) when needed in response to process-voltage-temperature variations. Embodiments include simulating critical paths (114) of typical memory cells (104) and readout circuits (102) in the SRAM. Applying a trigger signal to the critical path's word line input port (123) and comparing the critical path's output (125) to a reference latch signal (127) provides a sense of when to go high to the SRAM An indication of the supply voltage of the circuit.

Description

[0001] Claim of priority under 35 U.S.C. §119 [0002] The title of this patent application claimed on September 12, 2011 is "Apparatus for Adaptive Read Word-line Boosting in Multi-port SRAM (APPARATUS FOR ADAPTIVE READ WORD-LINE BOOSTING WITHIN A MULTI-PORT SRAM)" Priority to Provisional Application No. 61 / 533,647 of , which is assigned to the present assignee and is hereby expressly incorporated herein by reference. technical field [0003] This invention relates to electronic circuits and, more particularly, to static random access memories. Background technique [0004] Static Random Access Memory (SRAM) is a common type of non-volatile memory that has low power dissipation and is capable of high speed operation. [0005] An example of an SRAM memory cell is illustrated in Figure 5 middle. It is a so-called eight-transistor (8T) SRAM cell, where the eight transistors in the cell are labeled M1 through M8. exist Figure 5 In , the write word line is denoted WWL, t...

AI Technical Summary

Problems solved by technology

For example, the cell read current of weak bits may affect and degrade the performance of SRAM cache memory

Also, weak bits have higher voltage sensitivity due to higher threshold voltages, which can lead to worse performance degradation than performance degradation due to supply voltage noise

Images