System for reducing leakage current of SRAM (Static Random Access Memory) by self-adapting process voltage and temperature

A technology of static memory and process voltage, applied in the field of memory, can solve the problems of low area and power consumption overhead, low leakage SRAM can not adaptively and accurately adjust the SRAM power supply voltage, etc., to achieve resistance to power supply voltage fluctuations, simple structure, small area Effect

Active Publication Date: 2020-10-02
SOUTHEAST UNIV
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  • Abstract
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Problems solved by technology

[0004] The purpose of the present invention is to address the deficiencies of the above-mentioned background technology, to provide a system for reducing the leakage current of static memory SRAM through adaptive process voltage and temperature, and to fit the actual minimum data retention of SRAM through a process voltage and temperature monitoring module with a small area overhead Voltage, combined with the closed loop composed of the voltage regulation module, switch tube module and

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  • System for reducing leakage current of SRAM (Static Random Access Memory) by self-adapting process voltage and temperature
  • System for reducing leakage current of SRAM (Static Random Access Memory) by self-adapting process voltage and temperature
  • System for reducing leakage current of SRAM (Static Random Access Memory) by self-adapting process voltage and temperature

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Embodiment Construction

[0019] The technical solution of the invention will be described in detail below in conjunction with the accompanying drawings.

[0020] figure 1 It is the basic constituent unit of the SRAM array in the present invention, and is used for storing data 0 and 1. The bit line 102 is connected to the drain of the first NMOS transistor 104, the complementary bit line 103 is connected to the source of the second NMOS transistor 106, and the gate of the first NMOS transistor 104 is connected to the gate of the second NMOS transistor 106. To the word line 101, the source of the first NMOS transistor 104 is connected to the input terminal of the first inverter 107 and the output terminal of the second inverter 108, and the drain of the second NMOS transistor 106 is connected to the first The output end of the inverter 107 and the input end of the second inverter 108 are connected, the power supply of the first inverter 107 and the second inverter 108 is the power line 100, the first i...

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Abstract

The invention discloses a system for reducing leakage current of a static random access memory (SRAM) by self-adapting to process voltage and temperature, and belongs to the technical field of basic electrical elements. The system comprises a process voltage and temperature monitoring module, a voltage regulation module, a dummy load module, a switching tube module, a power tube module and a stateswitching control signal generation circuit module. After electrification, the whole system starts to work; the process voltage and temperature monitoring module outputs reference voltage values under the current process and temperature, and can resist certain power supply voltage fluctuation; in the switching process of entering sleep, the dummy load firstly works to stabilize the voltage regulation loop, pre-regulate the grid voltage of the power tube module, reduce the undershoot of the SRAM power supply voltage in the switching process, and then the dummy load is turned off; the SRAM canthoroughly enter a sleep mode after being regulated by the voltage regulation module and the power supply voltage is close to the output of the process voltage and temperature monitoring module. According to the invention, the SRAM power supply voltage can be adjusted to the optimal value in a self-adaptive manner under different process voltage and temperature conditions, so that the leakage current is reduced.

Description

technical field [0001] The invention discloses a system for reducing the leakage current of a static memory SRAM with an adaptive process voltage and temperature, relates to the memory technology, and belongs to the technical field of basic electrical components. Background technique [0002] In the actual application scenario of the chip, the chip may work in different modes, and common modes include high-performance mode, low-performance mode, and hold mode. In these common modes, the leakage current consumption of the chip is different. In order to prolong the working time of the battery, it is very important to reduce the leakage current. The suppression effect of the leakage current directly affects the life of the battery. Usually, the time of the system in the sleep or hold mode is much longer than the time of the dynamic work of the system. Therefore, reducing the leakage current in the hold mode is of great significance to the reduction of the overall leakage curren...

Claims

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Application Information

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IPC IPC(8): G11C11/412G11C11/417G11C5/14G01R19/00G01K13/00
CPCG11C11/4125G11C11/417G11C5/147G11C5/148G01R19/0084G01K13/00
Inventor 刘新宁邹为
Owner SOUTHEAST UNIV
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