A system for reducing the leakage current of static memory SRAM by adaptive process voltage and temperature
A technology of static memory and process voltage, applied in the field of memory, can solve the problems of low area and power consumption overhead, low leakage SRAM cannot self-adapt and accurately adjust the power supply voltage of SRAM, and achieve resistance to power supply voltage fluctuations, simple structure, and small area Effect
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[0019] The technical solution of the invention will be described in detail below in conjunction with the accompanying drawings.
[0020] figure 1 It is the basic constituent unit of the SRAM array in the present invention, and is used for storing data 0 and 1. The bit line 102 is connected to the drain of the first NMOS transistor 104, the complementary bit line 103 is connected to the source of the second NMOS transistor 106, and the gate of the first NMOS transistor 104 is connected to the gate of the second NMOS transistor 106. To the word line 101, the source of the first NMOS transistor 104 is connected to the input terminal of the first inverter 107 and the output terminal of the second inverter 108, and the drain of the second NMOS transistor 106 is connected to the first inverter 106. The output end of the inverter 107 and the input end of the second inverter 108 are connected, the power supply of the first inverter 107 and the second inverter 108 is the power line 10...
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