Automatic Phase Synchronization in Delay Locked Loop

Abstract

The tuning circuit may include a controller configured to determine a phase difference for a pair of signals generated at different points of a master delay line in the master-slave DLL circuit. One of the pair of signals travels through the slave delay line before the phase difference is determined. A programmed delay value for setting the phase delay of the slave delay line can be adjusted or tuned based on the phase difference.

Description

Background technique [0001] A master-slave delay locked loop (DLL) circuit may include a slave delay line configured to delay an input signal by a desired phase delay. As the structure of the DLL circuit as master-slave moves towards lower geometries, the phase delays associated with different slave delay lines from those included in different dies can vary significantly. Consequently, some slave delay lines may delay the received signal by an amount different from the desired phase delay. This difference or mismatch—called static phase error—can degrade or limit performance, such as reducing the timing margins for latching data. Contents of the invention [0002] In a first aspect, a circuit may be configured to adjust a programmed delay value for setting a phase delay of a slave delay line in a master-slave delay locked loop (DLL) circuit. The circuit may include a controller configured to determine a phase difference between a pair of master delay line signals generated...

AI Technical Summary

Problems solved by technology

This difference or mismatch—known as static phase error—can degrade or limit performance, such as reducing the timing margins for latching data

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