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Method and Apparatus for Arithmetic Decoding

An arithmetic coding and decoding technology, which is applied in digital video signal modification, electrical components, image communication, etc., can solve problems such as slow arithmetic decoding, overall decoder throughput bottleneck, and complexity

Inactive Publication Date: 2016-08-24
MEDIATEK INC
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

In addition, arithmetic decoding operations are usually more complex than other types of entropy decoding, such as variable length coding
Therefore, arithmetic decoding can be relatively slow compared to other decoding processes, thus becoming a bottleneck for the overall decoder throughput

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  • Method and Apparatus for Arithmetic Decoding

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Embodiment Construction

[0081] The following description is of the best contemplated mode of carrying out the invention. This description is given for the purpose of illustrating the general principles of the invention and should not be construed as limiting. The scope of the invention is best determined by reference to the appended claims.

[0082] Arithmetic coding is typically used for binary strings produced after prediction and / or quantization. In addition, various encoding parameters and system configuration information need to be transmitted. These encoding parameters and system configuration information will be binarized into binary strings. The arithmetic coded bit stream is then processed using a binarization procedure according to the selected binary code, such as Unary code, Huffman code and Exp-Golomb code. Arithmetic coding is usually applied to binary strings associated with certain syntax elements, such as Motion vector difference (MVD), coding unit (CU) partition mode, prediction ...

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Abstract

An apparatus and method for high-throughput entropy decoding in a video decoder are disclosed. The apparatus comprises an arithmetic decoding processing circuitry and a variable-length decoder (VLD). The arithmetic decoding processing circuitry receives a video bitstream through a bitstream input, applies arithmetic decoding to at least a portion of the video bitstream to derive one or more arithmetic-decoded binary strings containing no arithmetic encoded binary string, and stores the arithmetic-decoded binary strings in the storage device. The variable-length decoder (VLD) is coupled to the arithmetic decoding processing circuitry, the storage device and a VLD output. The variable-length decoder receives at least a portion of arithmetic-decoded bitstream when arithmetic-decoded bitstreams stored in the storage device are complete for a selected image unit, decodes at least a portion of arithmetic-decoded bitstream into one or more decoded syntax elements, and provides the decoded syntax elements through the VLD output.

Description

technical field [0001] The invention relates to an entropy decoder for compressing data. In particular, the present invention relates to the design of high-throughput arithmetic decoding of entropy-coded bit-streams generated by arithmetic coding. Background technique [0002] Video data requires a large amount of storage space for storage or a wide bandwidth for transmission. With the increasing high resolution and high frame rate, if video data is stored or transmitted in an uncompressed form, huge storage or transmission bandwidth requirements will be required. Therefore, video data is usually stored or transmitted in a compressed format using a video coding technique. Coding efficiency has been greatly improved by using newer video coding standards such as H.264 / AVC and the emerging HEVC (High Efficiency Video Coding) standard. In order to maintain manageable complexity, an image is often divided into multiple blocks, such as macroblock (Macroblock, MB) or largest cod...

Claims

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Application Information

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IPC IPC(8): H04N19/13H04N19/86H04N19/176H04N19/61H04N19/107H04N19/51
CPCH04N19/91H04N19/13H04N19/107H04N19/176H04N19/51H04N19/61H04N19/86
Inventor 郑佳韵张永昌
Owner MEDIATEK INC
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