A random verification method and device for a multi-core processor supporting accurate memory access detection

Abstract

The invention provides a random multi-core processor verification method and device supporting precise memory access detection. The method comprises the following steps of: (1), generating parallel programs having a memory access conflict as verification vectors by combining user constraint in a multi-core processor to be verified with an instruction library, operating the verification vectors, and recording a verification vector execution result and memory access operation time information; (2), according to the execution result and the memory access operation time information, performing a memory consistency design correctness check, and, if the memory consistency design of the multi-core processor to be verified accords with a memory consistency model, executing the step (3); and (3), feeding the verification vectors and the memory access operation time information into an instruction-stage simulator, executing the verification vectors by the instruction-stage simulator according to the memory access operation time information, comparing the result with an execution result after the multi-core processor is simulated, and continuously executing random verification of the multi-core processor if the comparison results are consistent.

Description

technical field [0001] The invention relates to the field of VLSI design verification, in particular to a multi-core processor random verification method and device thereof supporting accurate memory access detection. Background technique [0002] The semantics of the memory model of a single-core processor are intuitive, that is, a read operation to any memory unit will return the value written to the unit by the most recent write operation, and the write operation uniquely determines the result of subsequent read operations on the same unit . When random verification of a single-core processor is performed by a simulation method, the reference model is usually used to give the reference execution result of the verification vector, and the result of the reference model is compared with the actual RTL (register-transfer level) execution result to judge whether it is right or wrong , for a serial program in a single-core processor environment, the result of each run is uniqu...

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Problems solved by technology

[0005] However, the above method cannot solve the problem of correctness comparison in the simulation verification of multi-core processors. Even if it is proved that the directed graph of the parallel program memory access sequence of multi-core processors is acyclic, it can only show that the memory consistency design of multi-core processors conforms to The storage consistency model specification, and the multi-core processor memory access sequence and results in the case of conforming to the storage consistency model specification can still be non-unique. When the memory access instruction is randomly combined with more complex instructions in the parallel program, this access The non-uniqueness of the stored results will cause the state space explosion of the execution results, making it difficult to judge the correctness of the instruction execution results when the multi-core processor performs random simulation verification

[0006] Random verification technology is an important supporting technology in the processor simulation verification process. figure 1 The common framework of the processor random verification method is described in , the user constraint 102 is combined with the instruction library 101, the verification vector is generated by the random generation engine 103, and the generated verification vector is sent to the instruction level simulator 104 and the simulation of the design to be verified environment 105, and compare the execution results. When the comparison results are inconsistent, errors in the processor design can be detected. For multi-core processors, when memory access instructions are randomly combined with other complex instructions in parallel programs, access The non-uniqueness of the stored results will cause the state space explosion of the execution results, which makes it difficult to complete the result comparison link during the random verification, making it difficult to directly use the traditional random verification technology for multi-core processor simulation verification. This problem has not been resolved.

At present, the commonly used mode for verifying multi-core processors is: firstly use the traditional random verification technology to verify each processor core in the multi-core processor, then perform simulation verification for the on-chip network connecting each processor core, and finally store the multi-core processor system. Consistency verification, this multi-core processor verification mode often causes design error escape, especially when the multi-core processor storage consistency design is correct, and errors will occur when multi-core interleaved memory access and other instructions are mixed and executed, multi-core processor verification often Inability to accurately detect and locate errors

[0007] To sum up, in the current multi-core processor simulation verification, the non-uniqueness of memory access results causes the result state space explosion problem, which makes it difficult to complete the result comparison link during random verification, and cannot accurately detect and locate errors. In the actual operation of multi-core processor chips , due to the scheduling of the operating system and the randomness of shared memory access conflicts, the execution results of parallel programs cannot be uniquely determined

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