An Ethernet protocol analysis and trigger circuit and method in an oscilloscope
A technology of trigger circuit and protocol analysis, which is applied in the direction of instruments, measuring electrical variables, digital variable display, etc., can solve the problems of high cost, short decoding length, slow decoding speed, etc., and achieve the effect of low cost and fast decoding speed
Active Publication Date: 2018-11-20
THE 41ST INST OF CHINA ELECTRONICS TECH GRP
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Problems solved by technology
[0006] The purpose of the present invention is to solve the problems of high cost, slow decoding speed and short decoding length in view of the fact that the Ethernet protocol analysis and trigger function in the existing oscilloscope is mainly realized through the Ethernet receiving chip or software, and proposes a method through A receiving processing unit is set, and an Ethernet protocol analysis and triggering circuit and method in an oscilloscope is realized through the cooperation of the receiving processing unit and the existing hardware and circuits in the oscilloscope to realize Ethernet protocol analysis and triggering
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[0028] The specific embodiment of the present invention will be further described below in conjunction with accompanying drawing and specific embodiment:
[0029] Such as image 3 As shown, an Ethernet protocol analysis and trigger circuit in an oscilloscope includes a channel, a comparator, an analog-to-digital converter, and an FPGA. The data signals of the comparator and the analog-to-digital converter all flow to the FPGA, and a peak detection circuit is designed in the FPGA. Sampling data processing circuit, receiving speed reduction circuit, sampling clock generation circuit and storage control circuit, the signal of receiving speed reduction circuit flows to the peak detection circuit and sampling data processing circuit respectively, the signal of peak detection circuit flows to the channel, and the signal of sampling data processing circuit Flow to the storage control circuit, the receiving processing unit is also designed in the FPGA, and the receiving processing uni...
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The invention discloses an Ethernet protocol analysis and trigger circuit and method in an oscilloscope, and specifically relates to the technical field of testing. It solves the problems that the Ethernet protocol analysis and triggering functions in the existing oscilloscope are mainly realized through the Ethernet receiving chip or software, which has the disadvantages of high cost, slow decoding speed and short decoding length. The Ethernet protocol analysis and trigger circuit in the oscilloscope includes channels, comparators, analog-to-digital converters, and FPGA. The peak detection circuit, sampling data processing circuit, receiving speed reduction circuit, sampling clock generation circuit, and storage control circuit are designed in the FPGA. and a receiving processing unit, the receiving processing unit includes a decoding clock generation circuit and sequentially connected acquisition circuit, unwinding start detection circuit, unwinding circuit, preamble detection circuit, 5B / 4B encoding and decoding circuit and frame content detection analysis trigger circuit.
Description
technical field [0001] The invention belongs to the technical field of testing, and in particular relates to an Ethernet protocol analysis and trigger circuit and method in an oscilloscope. Background technique [0002] As the signals that the oscilloscope needs to test become more and more complex and have more and more functions, how to realize these functions with little or no increase in cost becomes particularly important. [0003] At present, the Ethernet protocol analysis and trigger functions in the oscilloscope are mainly realized by the Ethernet receiving chip or software. The solution of using the Ethernet receiving chip is as follows: figure 1 As shown, the receiving chip mainly realizes functions such as unwrapping, conversion from 5B encoding to 4B encoding, and synchronous clock extraction. What is sent to the FPGA is the processed trigger start frame delimiter, MAC address, and MAC Q-Tag control information. , MAC length / type, IP packet header and other inf...
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IPC IPC(8): G01R13/02
CPCG01R13/0209G01R13/0254
Inventor 邵成华向前杨江涛吴恒奎
Owner THE 41ST INST OF CHINA ELECTRONICS TECH GRP