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Method of forming fin for FinFET semiconductor device and the resulting device

A technology of fins and dielectric layers, applied in semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., can solve problems such as short circuits

Active Publication Date: 2016-11-23
GLOBALFOUNDRIES U S INC MALTA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Air gaps 250 represent undesirable trenches in the structure that can lead to significant defects such as shorts during subsequent processing

Method used

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  • Method of forming fin for FinFET semiconductor device and the resulting device
  • Method of forming fin for FinFET semiconductor device and the resulting device
  • Method of forming fin for FinFET semiconductor device and the resulting device

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Embodiment Construction

[0034] Various exemplary specific embodiments of the present invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. Of course, it will be appreciated that in developing any such actual embodiment, many implementation-specific decisions must be made in order to achieve the developer's specific goals, such as compliance with system-related and business-related constraints that will Varies with implementation. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.

[0035]The subject matter of this patent will now be described with reference to the accompanying drawings. Various structures, systems and devices are shown in the drawings for purposes of illustration only and to not obscure the disclosure with details that are ...

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Abstract

A method of forming fins for FinFET semiconductor devices and the resulting device are provided; the method includes forming a plurality of fins above a substrate, forming at least one dielectric material above and between the plurality of fins, and forming a mask layer above the dielectric material. The mask layer has an opening defined therein. At least one etching process is performed to remove a portion of the at least one dielectric material exposed by the opening so as to expose a top surface portion and sidewall surface portions of at least one fin in the plurality of fins. The at least one dielectric material remains above the substrate adjacent the at least one fin. An etching process is performed to remove the at least one fin.

Description

technical field [0001] The present disclosure relates generally to the fabrication of integrated circuits and, more particularly, to various methods of forming fins for FinFET semiconductor devices and semiconductor devices therefor. Background technique [0002] In modern integrated circuits such as microprocessors, memory devices and the like, a very large number of circuit elements, especially transistors, are provided on a limited chip area. Transistors come in various shapes and forms, such as planar transistors, FinFETs, nanowire devices, and more. These transistors are typically NMOS (NFET) or PMOS (PFET) type devices, where the "N" and "P" designations are based on the type of dopant used to create the source / drain regions of the device. The so-called CMOS (Complementary Metal Oxide Semiconductor) technology or products refer to integrated circuit products manufactured using NMOS and PMOS transistor devices. Regardless of the physical configuration of the transisto...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/336
CPCH01L29/66795H01L21/823821H01L21/823431H01L21/764H01L21/76224H01L29/6681H01L21/762
Inventor 成敏圭谢瑞龙
Owner GLOBALFOUNDRIES U S INC MALTA