Multi-track and multi-measurement-position parallel testing and sorting device for integrated circuit chips

A sorting device and integrated circuit technology, applied in sorting and other directions, can solve the problems of scattered IC chip packaging and low efficiency, and achieve the effects of compact structure, improved efficiency, and automatic control

Active Publication Date: 2017-01-11
FUZHOU PALIDE ELECTRONICS TECH
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the existing sorting methods for integrated circuit chips are likely to cause scattered packaging of integrated circuit chips, resulting in low efficiency

Method used

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  • Multi-track and multi-measurement-position parallel testing and sorting device for integrated circuit chips
  • Multi-track and multi-measurement-position parallel testing and sorting device for integrated circuit chips
  • Multi-track and multi-measurement-position parallel testing and sorting device for integrated circuit chips

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Embodiment Construction

[0022] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

[0023] like Figure 1~6As shown, the embodiment of the present invention provides a multi-track multi-positioning parallel testing and sorting device for integrated circuit chips, including a frame 1, the upper surface of the frame 1 is provided with a flat plate for supporting the feeding mechanism 2, The front side of the frame 1 is provided with an inclined panel 11, and the inclined panel 11 is sequentially provided with a feeding test mechanism 3, a sorting buffer mechanism 4 and a receiving mechanism 5 from top to bottom; It includes 2N feeding track grooves 30 arranged at the upper end of the inclined plate 11 at uniform intervals along the lateral direction; each feeding track groove 30 entrance is respectively equipped with a lifting tube turning mechanism 6 that cooperates with the feeding mechanism 2, and the feeding A first infrare...

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Abstract

The invention relates to a multi-track and multi-measurement-position parallel testing and sorting device for integrated circuit chips. The multi-track and multi-measurement-position parallel testing and sorting device for the integrated circuit chips comprises a rack which is provided with a flat panel, and an oblique panel is arranged on the front side of the rack. The oblique panel is provided with a feeding testing mechanism, a sorting and caching mechanism and a collecting mechanism sequentially from top to bottom, wherein the feeding testing mechanism comprises 2N feeding track grooves formed in the upper end of the oblique panel at uniform intervals in the transverse direction; the sorting and caching mechanism comprises N distribution shuttles, a transverse transferring mechanism, a qualified product automatic-sorting groove set, and N unqualified product manual-sorting groove sets arranged beside the qualified product automatic-sorting groove set; and the collecting mechanism comprises manual pipe-drawing collecting mechanisms arranged below the unqualified product manual-sorting groove sets, and automatic pipe-replacing collecting mechanisms arranged below the qualified product automatic-sorting groove set. The multi-track and multi-measurement-position parallel testing and sorting device for the integrated circuit chips has the beneficial effects that detection is carried out through the 2N feeding track grooves simultaneously, and the sorting and measuring efficiency is improved.

Description

technical field [0001] The invention relates to the field of integrated chip sorting, in particular to a multi-track multi-position measuring and parallel testing sorting device for integrated circuit chips. Background technique [0002] Integrated circuit chips must undergo rigorous testing before leaving the factory. The test items include various performance parameters of integrated circuit chips, such as current and voltage. People need to screen out the integrated circuit chips whose test results are not within the qualified range, and classify the integrated circuit chips with different test results. At present, automatic sorting machines are generally used instead of manual sorting. However, the existing sorting method for integrated circuit chips is likely to cause scattered packaging of integrated circuit chips, resulting in low efficiency. Contents of the invention [0003] The object of the present invention is to provide a multi-track multi-positioning parall...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): B07C5/344B07C5/02B07C5/38
CPCB07C5/02B07C5/344B07C5/38
Inventor 谢名富吴成君
Owner FUZHOU PALIDE ELECTRONICS TECH
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