Static superscale DSP cycle simulation method

A simulation method and superscalar technology, applied in the field of DSP cycle simulation, can solve the problems of inaccuracy and slow speed of DSP simulation method

Active Publication Date: 2017-01-11
BEIJING INST OF CONTROL & ELECTRONICS TECH
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  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The purpose of the present invention is to provide a static superscalar DSP cycle simulation method to solve the problems of imprecise and slow speed in the existing DSP simulation method

Method used

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  • Static superscale DSP cycle simulation method
  • Static superscale DSP cycle simulation method
  • Static superscale DSP cycle simulation method

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Experimental program
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Embodiment Construction

[0031] The specific steps of a static superscalar DSP cycle simulation method are:

[0032] Take the static superscalar DSP TS101 of ADI's 8-stage pipeline as an example,

[0033] The first step is to build a static superscalar DSP cycle simulation system

[0034] Static superscalar DSP cycle simulation system, including instruction preparation module and instruction execution module.

[0035] The functions of the instruction preparation module are: analyze the control flow relationship and data flow relationship between instructions, control the instruction sequence and pipeline progress entering the pipeline, and realize the simulation of DSP instruction timing, that is, the simulation of TS101 instruction timing.

[0036] The functions of the instruction simulation module are: translate the instruction semantics, update the DSP software visible register status and internal pipeline status, and realize the simulation of the DSP instruction set function, that is, the simulat...

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Abstract

The invention discloses a static superscale DSP cycle simulation method. A static superscale DSP cycle simulation system including an instruction preparation module and an instruction execution module is constructed; the instruction preparation module sets an initial value, acquires an instruction, determines the number of deferred cycles, determines the number of pause cycles and simulates clock propulsion; the instruction simulation module executes function simulation; a mathematical model of a superscale DSP cycle state is constructed from the view of time sequence; by time sequence simulation, an accurate state in a cycle when a DSP assembly line is paused; time sequence calculation mainly includes seeking of a maximum or minimum value and intersection operation which can be efficiently realized by bitwise operation; therefore, copying expense on a large number of register transfer levels and search expense on a register dependency sheet are avoided; the simulation calculation amount is relatively low, and the problems that a superscale DSP simulation method is inaccurate and relatively low in speed during DSP real-time software simulation test at the present are solved.

Description

technical field [0001] The invention relates to a DSP cycle simulation method, in particular to a static superscalar DSP cycle simulation method. Background technique [0002] Processor simulation method is an important means of processor architecture evaluation and software simulation test. According to the degree of reality of simulation, it can be divided into two categories: instruction cycle-level accurate simulation method and instruction function-level accurate simulation method. The evaluation of processor architecture generally adopts the accurate simulation method at the instruction cycle level. By accurately modeling the internal microstructure, it can describe the cycle state of instruction execution, but the simulation calculation is large; the software simulation test generally adopts the instruction function level accurate simulation method. Model software-related processor states from a functional point of view, with a small amount of simulation calculation, ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
Inventor 陈俊文甘志强冯云程高辉
Owner BEIJING INST OF CONTROL & ELECTRONICS TECH
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