A data communication synchronization method based on a shared memory

A shared memory and data communication technology, applied in memory systems, electrical digital data processing, instruments, etc.

Active Publication Date: 2017-02-15
FUDAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

What the present invention needs to solve is how to ensure the synchronization of data communication between multi-cores without introducing cache, that is, the data communication between processors is only realized through shared memory

Method used

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  • A data communication synchronization method based on a shared memory
  • A data communication synchronization method based on a shared memory
  • A data communication synchronization method based on a shared memory

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Experimental program
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Embodiment Construction

[0023] Below in conjunction with accompanying drawing, the present invention will be further described.

[0024] The invention is based on the realization of a parallel GPDT algorithm on a multi-core SOC. First, each data block that needs to be shared is allocated an address space in the shared memory. For the communication process of the result splicing, the shared address space is divided according to the workload assigned to each processor, so that each processor and the divided Each processor only needs to write the data blocks calculated by the core into the corresponding address space of the core; for the communication process of result accumulation, there is no need to divide the address space, and each processor from The same starting address starts overwriting, such as figure 1 shown.

[0025] Design a 2-bit identification bit for the shared data block corresponding to each processor to indicate whether the data block is readable and writable for other processors. T...

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Abstract

The invention belongs to the technical field of integrated circuit design, and in particular relates to a data communication synchronization method based on a shared memory. In a multi-core SoC system based on bus interconnection, the data communication between multiple processors is generally realized by a shared memory. The method realizes the parallel GPDT algorithm by using the multi-core SoC and combines or adds up calculation results of the processors by using the share memory in matrix operations to construct a complete result. For communication processes requiring result combination, a shared address space is reasonably divided according to the workload for each processor so that the processors are corresponding to address space segments obtained after division in a one-to-one manner, and the calculation results are written into the corresponding address spaces; for communication processes requiring result add-up, the processers write data into the same address space in a covering manner. To avoid data collision, the invention provides the data synchronization method of identifier detection-identifier modification-storage access-identifier restoration, so that the data collision occurrence probability is greatly reduced.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit design, in particular to a data communication synchronization method based on a shared memory. Background technique [0002] In a multi-core processor with shared storage, a cache structure is generally introduced to cache the data in the shared storage space locally, and use its own structural characteristics to speed up the process of multi-core data acquisition. Since the memory view seen by each processor is obtained through the local cache, different processors may obtain different data values ​​for the data in the same storage location. In the design of multi-core processors, a cache consistency maintenance mechanism must be introduced to ensure that each processor can always obtain the latest written value for the read operation of the same location in the memory. With the increasingly complex data interaction modes between multi-cores (multi-threads), whether an efficient cache...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/0844
CPCG06F12/0844
Inventor 韩军轩四中袁腾跃曾晓洋
Owner FUDAN UNIV
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