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vliw-type instruction bundle structure and processors suitable for processing the instruction bundle

A technology of processors and processing tools, applied in instruction analysis, concurrent instruction execution, electrical digital data processing, etc.

Active Publication Date: 2019-04-05
卡尔雷公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, this solution also requires a multiplexer with a large number of input
In particular, the multiplexer MX44 may need to delay the processing of the instruction bundle by one clock cycle

Method used

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  • vliw-type instruction bundle structure and processors suitable for processing the instruction bundle
  • vliw-type instruction bundle structure and processors suitable for processing the instruction bundle
  • vliw-type instruction bundle structure and processors suitable for processing the instruction bundle

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Experimental program
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Embodiment Construction

[0031] According to an embodiment, the compiler generates VLIW instruction bundles by sorting the basic instructions in each VLIW instruction bundle starting from the first byte of the basic instructions, each VLIW instruction bundle includes one or more basic instructions, each basic Instructions are formed of one or more bytes. Thus, each bundle of VLIW instructions includes bytes of the first level of all elementary instructions of the bundle, followed by bytes of a possible second level, and so on. The bytes of each level are ordered according to the order they are assigned to the processing units. Therefore, only the order of the bytes is placed in the VLIW instruction bundle, not the exact position of the bytes in the bundle.

[0032] Figure 5 Shown are the processing units PU1-PU4 of the processor PRC and the input circuits INC for the processing units PU1-PU4, which are adapted to process the bundle of instructions. The input circuit INC comprises instruction regist...

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PUM

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Abstract

The invention relates to a processor comprising a plurality of processing units (PU1-PU4) for parallel processing of a plurality of elementary instructions (Pj), each elementary instruction (Pj) comprising one or more bytes (Pj[1] , Pj[2]), each byte has a level in the basic instruction; and an input circuit (INC, INC'), the input circuit (INC, INC') is configured to receive an instruction bundle including a plurality of basic instructions ( IW), and all the words of the first level (Pj[1]) of the elementary instructions of the bundle to the processing unit before transferring the bytes of the second level (Pj[2]) of the elementary instructions of the bundle to the processing unit section, bytes at the same level are ordered according to the target processing unit for each byte.

Description

technical field [0001] The present invention relates to Very Long Instruction Word (VLIW) processors, and in particular to Variable Length Instruction Bundle processors. Background technique [0002] The processor includes a CPU having multiple processing units for executing multiple instructions in parallel. A VLIW instruction bundle may include multiple primitive instructions targeting different processing units of a CPU. Thus, instruction bundles for the processor can be typically between 64 and 128 bits in length, or even 256 bits or more. [0003] In some VLIW processors, the distribution of the elementary instructions to the instruction bundle among the CPU processing elements is usually performed in the same order. Fig. 1 shows the input circuit INC1 of the processing units PU1, PU2, PU3, PU4 of such a processor. The circuit INC1 comprises registers R01-R04 and R11-R14 designed to receive elementary instructions of the instruction bundle. Registers R0j, R1j are co...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/30G06F9/38
CPCG06F9/30149G06F9/3853G06F8/445G06F9/3856G06F9/3885
Inventor R·阿里格耐克V·雷B·杜邦德丁辰
Owner 卡尔雷公司