Implementation method of chip of PVLAN in stacked mode

An implementation method and chip technology, applied in the direction of data exchange, digital transmission system, electrical components, etc. through path configuration, to achieve the effect of reducing the use cost, flexible and efficient application, and reducing the number of devices

Active Publication Date: 2017-05-17
SUZHOU CENTEC COMM CO LTD
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  • Claims
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[0010] But at this stage there is no tech...

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  • Implementation method of chip of PVLAN in stacked mode
  • Implementation method of chip of PVLAN in stacked mode
  • Implementation method of chip of PVLAN in stacked mode

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Embodiment 2

[0088] The difference between Embodiment 2 and Embodiment 1 is that the outbound port VLAN filtering rules are configured globally, that is, each chip participating in the stack has VLAN filtering rules in the outbound direction of the ports of all the chips participating in the stacking. In this way, the ingress chip can perform the VLAN filtering rule check in the outbound direction of the port to know whether to discard the packet. If it is discarded, the ingress chip will perform the discarding action instead of the destination and egress chip to perform discarding, which can reduce aggregation (stacking) Port bandwidth pressure.

[0089] The configuration of port VLAN allocation and VLAN filtering rules in this solution is the same as that in the above-mentioned embodiment 1, and the processing of the message is also carried out correspondingly according to the VLAN filtering rules. The specific configuration content is described above, and will not be repeated here. .

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Abstract

The invention provides an implementation method of a chip of PVLAN (Private VLAN) in a stacked mode. The implementation method of a chip of PVLAN in a stacking mode is characterized by distributing corresponding VLANS for ports of a stacked chip; setting VLAN filtering rules for the in direction and the out direction for the ports participating PVLAN; and after the chip receives a massage, processing the message according to the VLAN filtering rules on the out port. The implementation method of a chip of PVLAN in a stacked mode greatly expands the application range of the PVLAN technology so as to enable application of PVLAN to be more flexible and efficient.

Description

technical field [0001] The invention relates to a PVLAN (Private VLAN, dedicated virtual local area network) technology, in particular to a chip implementation method of PVLAN in a stacking mode. Background technique [0002] Stacking technology is a common technology for extending ports on Ethernet switches, which can be stacking at the switch level or at the switching chip level. The switches (switching chips) participating in the stack are connected through topologies such as ring (ring), tree (tree), and fullmesh (full mesh), and are regarded as one device on the management plane. [0003] PVLAN (Private VLAN) is a technology used to solve the effective allocation and rational utilization of VLAN (Virtual Local Area Network) resources in the operator network. The basic principle of this technology is to assign two different attributes to the VLAN, namely Primary VLAN ( Primary VLAN, which communicates with the operating network) and Secondary VLAN (auxiliary VLAN, which...

Claims

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Application Information

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IPC IPC(8): H04L12/46H04L12/931H04L12/935H04L49/111
CPCH04L12/4641H04L49/30H04L49/354
Inventor 张国颖杨曙军单哲
Owner SUZHOU CENTEC COMM CO LTD
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