Array substrate and liquid crystal display panel
A technology of array substrate and color filter substrate, applied in nonlinear optics, instruments, optics, etc., can solve problems such as loss of aperture ratio, and achieve the effect of avoiding loss of aperture ratio and realizing color shift compensation.
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment 1
[0038] figure 2 It is a cross-sectional view of a partial structure of the array substrate in an embodiment of the present invention. Combine below figure 2 The specific structure of the array substrate is described in detail.
[0039] The array substrate includes a plurality of scan lines, a plurality of data lines, a plurality of auxiliary electrodes, and a plurality of pixel unit pairs that do not overlap each other.
[0040] Among them, a plurality of pixel unit pairs that do not intersect each other means that each pixel unit pair and each pixel unit pair are completely independent of each other. Moreover, each pair of pixel units has the same structure as each pair of pixel units. Specifically, each pair of pixel units includes two adjacent pixel units, which are respectively defined as a first pixel unit and a second pixel unit.
[0041] The first pixel unit includes a first thin film transistor and a first pixel electrode. Wherein, the gate of the first thin film transis...
Embodiment 2
[0068] In this embodiment, the positions of the first scan line GATE1 and the second scan line GATE2 in the first embodiment are further optimized.
[0069] The pixel array structure in the prior art is such as Image 6 As shown, the pixel is above the gate line. Take the first pixel PIXEL1 (not shown in the figure), the first gate line GATE1, the second pixel PIXEL2 (not shown in the figure), and the second gate line GATE2 as an example. In the prior art, the first pixel is disposed above the first gate line GATE1 (first scan line), and the second pixel is disposed above the second gate line GATE2 (second scan line).
[0070] In this embodiment, the first scan line GATE1 and the second scan line GATE2 are preferably arranged adjacently. Specifically, according to Figure 7 As shown, the adjacent first gate line GATE1 and second gate line GATE2 are arranged together. The first pixel PIXEL1 is disposed above the first gate line GATE1, and the second pixel PIXEL2 is disposed below ...
Embodiment 3
[0073] This embodiment further optimizes the auxiliary electrode in the first or second embodiment. The projection of the auxiliary electrode on the metal layer where the scan line is located completely coincides with the first scan line and the second scan line.
[0074] Specifically, the auxiliary electrode preferably includes a first auxiliary electrode 801 and a second auxiliary electrode 802. Wherein, the first auxiliary electrode 801 and the second auxiliary electrode 802 are both connected to the drain of the first pixel unit (that is, the first pixel electrode of the first image unit). In addition, both ends of the first auxiliary electrode 801 are respectively aligned with both ends of the first scan line GATE1, and both ends of the second auxiliary electrode 802 are respectively aligned with both ends of the second scan line GATE2, such as Figure 8 Shown. Further, the first auxiliary electrode 801 and the first scan line GATE1 constitute the first coupling capacitor i...
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More