Accurate, fast and low-input fpga delay estimation method

A delay estimation and fast technology, applied in computing, instrumentation, biological neural network model, etc., can solve problems such as neural network dependence

Inactive Publication Date: 2019-12-27
TIANJIN UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, this method is overly dependent on the neural network, and requires a large amount of data support to obtain high-precision delay estimation results, and requires a lot of time in the early stage

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  • Accurate, fast and low-input fpga delay estimation method
  • Accurate, fast and low-input fpga delay estimation method
  • Accurate, fast and low-input fpga delay estimation method

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Embodiment Construction

[0061] The invention provides an FPGA circuit delay estimation method based on a neural network that integrates architecture-level and transistor-level parameters, which can be combined with an architecture exploration process to speed up architecture exploration while ensuring accuracy. The specific technical solutions are as follows:

[0062] 1) Determine the fitting parameter ɑ and the effective mobility μ.

[0063] 2) Equivalent each sub-circuit in the FPGA to an RC model, and determine the load capacitance of each type of transistor in each sub-circuit based on the FPGA architecture parameters.

[0064] 3) According to the determined fitting parameters ɑ, effective mobility μ and load capacitance and other parameters, respectively establish a delay model for each sub-circuit in the FPGA, namely the FPGA-macro delay model.

[0065] 4) Collect training data, analyze and normalize it.

[0066] 5) Combine the FPGA-macro delay model with the neural network, establish a KBNN ...

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Abstract

The invention relates to the field of FPGA architecture optimization. In order to fully consider the key parameters affecting circuit delay, it allows collaborative exploration of the variability of architecture-level parameters and transistor-level parameters in the FPGA architecture design stage, which not only reflects and maintains the physical meaning between parameters, but also Reduce the amount of training data for neural networks to achieve fast, accurate, and low-input latency estimation. For this reason, the present invention, the FPGA time-delay estimation method of accurate fast low investment, steps are as follows: 1) determine fitting parameter α and effective mobility μ; 2) determine the load capacitance of each type transistor in each sub-circuit; 3) Establish the FPGA-macro delay model for each sub-circuit in the FPGA; 4) analyze and normalize; 5) solve the weight Ω and Φ and the number m of hidden neurons, so that the training error E t and validation error E v minimum. The invention is mainly applied to design and manufacture occasions.

Description

technical field [0001] The invention relates to the field of FPGA architecture optimization, in particular to an FPGA delay calculation model. Specifically, it involves an accurate, fast and low-cost FPGA delay estimation method. Background technique [0002] With the development of the diversity of applications, the architecture of FPGA is constantly changing, and more and more time is spent on architecture exploration. Traditional methods require extensive experimentation to determine an FPGA architecture that meets latency requirements. Architectural designers need to use circuit simulation tools to measure critical path delays under each FPGA architecture, and then use place-and-route tools to simulate the delays mapped from the benchmark circuit onto the FPGA architecture, and evaluate the architecture performance based on the results. In fact, it is impossible to explore all architectural designs with this experimental approach, as it would take enormous effort and t...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/50G06N3/063
CPCG06F30/3312G06N3/065
Inventor 钱涵晶刘强
Owner TIANJIN UNIV
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