A Multi-channel Pipeline FIR Filter

A filter and multi-channel technology, applied in the field of filters, can solve the problems of low computing efficiency, and achieve the effects of easy expansion of order, simple cascading method, and high computing efficiency

Active Publication Date: 2020-01-10
CHINA ELECTRONICS TECH GRP CORP NO 14 RES INST
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Obviously, for a multiplier with a main frequency of 1GHz, when processing 200MHz input data, there will be 80% of the time in an idle state, and the operation efficiency is extremely low.

Method used

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  • A Multi-channel Pipeline FIR Filter
  • A Multi-channel Pipeline FIR Filter
  • A Multi-channel Pipeline FIR Filter

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Embodiment Construction

[0017] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0018] Firstly, the data of M channels input in parallel are time-divisionally merged into one channel, and then a zero-order filter unit and cascaded N-1 general-purpose filter units are used to perform multi-channel pipeline N-order FIR filtering operations on the channel data, and a total of Consume N multipliers and N-1 adders, and finally divide the operation results into M channels for parallel output. The structural block diagram is as follows figure 1 shown. Among them, s_axi_data_i is the i-th input data, m_axi_data_i is the i-th output data after the calculation is completed, i=0,1,...M-...

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Abstract

The invention discloses a multi-channel pipeline FIR filter, including a channel merging device, a zero-order filtering unit, a plurality of universal filtering units connected in series and a channel splitting device. M paths of input data pass through the channel merging device and are merged into one path to be output; a path of output signal of the zero-order filtering unit enters a buffering shifter, after buffering shifting, enters a second multiplier, multiplication operation is carried out on the output signal and an output signal of a second coefficient storage unit, a result is output to a multiplication output register block, a delayed signal and the other path of output signal of the zero-order filtering unit are added through an adder, and are then output to an addition output register block; and the channel splitting device is used for extracting parallel M paths of data from serial filtering signals to be output. The multi-channel pipeline FIR filter provided by the invention has high operation efficiency, supports input data interruption transmission, has a simple cascade mode, the order is easy to expand, and the universality is high.

Description

technical field [0001] The invention relates to the technical field of filters, in particular to a multi-channel pipeline FIR filter. Background technique [0002] With the increasing demand for wideband systems in the fields of radar and communication, wideband digital array processing technology is widely used. For a broadband digital array system, in order to compensate for the mismatch of frequency response between channels, a digital FIR equalization filter needs to be connected in series in each channel to make the frequency response of all channels consistent. In order to ensure the real-time performance of the system, the digital FIR equalization filter is usually realized by FPGA or dedicated ASIC. [0003] In the traditional N-order FIR time domain, pipeline calculations are often realized by connecting N multiply-adders in series, and the main frequency of the multiply-adders is consistent with the effective input data rate. However, because the actual data rate...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03H17/06
CPCH03H17/06H03H2017/0081
Inventor 李世平陈铠周海斌何国强
Owner CHINA ELECTRONICS TECH GRP CORP NO 14 RES INST
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