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GOA drive circuit and liquid crystal display panel

A driving circuit and driving unit technology, applied in static indicators, instruments, etc., can solve problems such as poor charging, poor display effect and quality, and high level, so as to improve quality, improve poor charging, and avoid poor charging Effect

Active Publication Date: 2017-08-04
TCL CHINA STAR OPTOELECTRONICS TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] However, in the existing GOA drive circuit, when the trigger units of several GOA drive units are triggered by the start signal (STV, Start Vertical), since the first K scan clocks (CK, Clock) are high-level periods, the The signal is always at a high level, thus causing the first K scan control signal Q(k) points (such as figure 2 ) potential is weakened by the coupling (Couple) effect of the bootstrap capacitor, which makes it take a long time for the first K gate lines (Gate) to reach the required high potential, resulting in poor charging, which in turn adversely affects the display effect and quality of the display influences

Method used

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  • GOA drive circuit and liquid crystal display panel
  • GOA drive circuit and liquid crystal display panel
  • GOA drive circuit and liquid crystal display panel

Examples

Experimental program
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Effect test

Embodiment 1

[0031] figure 1 is a schematic structural diagram of a GOA drive circuit with H scan clocks in an embodiment of the present invention, where H is the number of scan clocks in the GOA drive circuit 200, and H is an integer greater than 0. Such as figure 1 As shown, the driving circuit 200 includes a plurality of GOA driving units 210, and all the GOA driving units 210 are connected in sequence. Specifically, the output signal of the upper-level GOA driving unit 210 is used as the trigger signal of the lower-level GOA driving unit 210 , and the trigger signal of the first-level GOA driving unit 210 is generated by a trigger clock. Combine below figure 1 The specific structure of this drive circuit 200 will be described in detail.

[0032] Firstly, the structure of the first-level GOA driving unit 210 is described. The main structure of the first-level GOA driving unit 210 includes a trigger unit 211 , an output unit 212 and a pull-down unit 213 .

[0033] The trigger unit...

Embodiment 2

[0046] In view of the problem that the output signal of the GOA drive circuit in the prior art will be significantly attenuated when too many GOA drive units are cascaded, this embodiment improves the structure of the GOA drive circuit, such as figure 2 shown. figure 2 It is a schematic structural diagram of the GOA driving circuit 300 in this embodiment, which has N scan clock signals, where N is an integer greater than 0. The GOA drive circuit 300 includes a plurality of GOA drive units 310, wherein the trigger units 311 of the first N / 2 GOA drive units 310 are all triggered by the start signal STV, and the output signal of the mth GOA drive unit 310 is used as the m+Nth / 2 trigger signals of the driving unit 310 . Wherein, m is an integer satisfying 0figure 2 The structure of the GOA driving circuit 300 is further improved, so as to improve the poor charging of the first N / 2-1 scanning lines and improve the quality of the display image.

[0047] image 3 is a schematic s...

Embodiment 3

[0066] This embodiment further optimizes the number of scan clocks in the second embodiment.

[0067] Based on the second embodiment, this embodiment further limits the number of scan clocks. Preferably, the number of scan clocks N=8, such as Figure 4 shown. Figure 4 is a schematic structural diagram of a GOA driving circuit 500 with eight scan clocks in an embodiment of the present invention. Such as Figure 4 As shown, the GOA driving circuit 500 includes a plurality of GOA driving units 510 . Specifically, the trigger signals of the first three GOA drive units 510 are generated by trigger clock control, the trigger signal of the fourth GOA drive unit 510 is the turn-on signal STV, and the output signal of the mth GOA drive unit 510 is the m+4th The trigger signal of a GOA driving unit 510. Combine below Figure 4 The specific structure of this drive circuit 500 will be described in detail.

[0068] First of all, since the structures of the first three GOA drive uni...

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Abstract

The invention discloses a GOA drive circuit which comprises a plurality of GOA drive units. Each trigger unit in the first K GOA drive units includes a first thin film transistor and a second thin film transistor, wherein the gate of the first thin film transistor is connected with a trigger clock corresponding to the trigger unit, the drain of the first thin film transistor is connected with a start signal, the source of the first thin film transistor is connected with the gate and the drain of the second thin film transistor, the source of the second thin film transistor is connected with the control end of an output unit connected with the trigger unit, K is an integer greater than 0, and the trigger clock is configured to make the trigger unit closed when the scan clock of the output unit is at a high potential. The GOA drive circuit of the invention can improve the situation of poor charging of the first K scanning lines, and improve the quality of display pictures.

Description

technical field [0001] The invention relates to the field of display technology, in particular to a GOA driving circuit and a liquid crystal display panel. Background technique [0002] Under the background that liquid crystal displays are constantly developing toward low-cost and high-quality, Gate Driver On Array (GOA, Gate Driver On Array) technology has been widely used due to its advantages of low cost and high integration. [0003] However, in the existing GOA drive circuit, when the trigger units of several GOA drive units are triggered by the start signal (STV, Start Vertical), since the first K scan clocks (CK, Clock) are high-level periods, the The signal is always at a high level, thus causing the first K scan control signal Q(k) points (such as figure 2 ) potential is weakened by the coupling (Couple) effect of the bootstrap capacitor, which makes it take a long time for the first K gate lines (Gate) to reach the required high potential, resulting in poor chargi...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G09G3/36
CPCG09G3/3677
Inventor 冯托徐向阳
Owner TCL CHINA STAR OPTOELECTRONICS TECH CO LTD