Semiconductor device and manufacturing method thereof

Abstract

Embodiments of the present invention provide semiconductor devices and methods of manufacturing the same. The semiconductor device includes a first channel layer disposed above the substrate, a first source / drain region disposed above the substrate, a channel layer disposed on and wrapping each first channel layer A gate dielectric layer and a gate electrode layer disposed on the gate dielectric layer and wrapping each first channel layer. Each of the first channel layers includes a semiconductor line made of a first semiconductor material. The semiconductor line extends to the first source / drain region. The semiconductor lines in the first source / drain are surrounded by the second semiconductor material.

Description

[0001] Cross References to Related Applications [0002] This application claims priority to US Provisional Patent Application No. 62 / 261,267, filed November 30, 2015, the entire contents of which are hereby incorporated by reference. technical field [0003] Embodiments of the present invention relate to semiconductor integrated circuits, and more particularly, to semiconductor devices having a gate-all-around structure and methods of manufacturing the same. Background technique [0004] As the semiconductor industry enters nanotechnology process nodes in the pursuit of higher device density, higher performance, and lower cost, challenges from manufacturing and design issues have given rise to applications such as the Multi-Gate FinFET (Multi-Gate FinFET) FET) including fin FET (Fin FET) and gate all around (GAA) FET). In a Fin FET, the gate electrode is adjacent to three sides of the channel region, with a gate dielectric layer interposed between the gate electrode and th...

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Problems solved by technology

Unfortunately, on the fourth side, the bottom of the channel is far from the gate electrode and thus not under the tight control of the gate

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