Contacting SOI substrates

Abstract

The invention relates to contacting SOI substrates. An integrated circuit is provided including a semiconductor bulk substrate, a buried oxide layer formed on the semiconductor bulk substrate, a plurality of cells, each cell having a transistor device, formed over the buried oxide layer, a plurality of gate electrode lines running through the cells and providing gate electrodes for the transistor devices of the cells, and a plurality of tap cells configured for electrically contacting the semiconductor bulk substrate and arranged at positions different from positions below or above the plurality of cells having the transistor devices.

Description

technical field [0001] The present invention relates generally to the field of integrated circuits and semiconductor devices, and more particularly to the formation of contacts to bulk semiconductor substrates of SOI devices. Background technique [0002] Manufacture of advanced integrated circuits such as CPU (central processing unit), memory device, ASIC (application specific integrated circuit) etc. requires forming a large number of circuit elements on a given chip area according to a specific circuit layout. In a variety of electronic circuits, field effect transistors represent an important type of circuit element that substantially determines the performance of the integrated circuit. In general, a variety of fabrication method technologies are currently implemented to form field effect transistors (FETs), where, for many types of complex circuits, MOS technology is superior in terms of speed of operation and / or power consumption and / or cost efficiency. It has become...

AI Technical Summary

Problems solved by technology

In practice, the formation of the poly ridge 19 cannot be properly controlled because the focal point of the lithographic apparatus used is at the location where the poly gate 14a must be formed

On the other hand, due to the regular grid of polycrystalline lines formed, the formation of polycrystalline ridges 19 cannot be avoided

The undesired formation of polycrystalline ridges 19 in this opening of the BOX layer 13 leads to wafer contamination, since the unstable polycrystalline ridge structures 19 are prone to fracture during further processing

[0009] In view of the above situation, the present invention provides a technique for forming substrate contacts to avoid wafer contamination caused by polycrystalline residues caused by the formation of thin polycrystalline ridges in large BOX openings in prior art manufacturing methods

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