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data erasure method

A technology of data erasure and erasure verification, which is applied in the field of data erasure of flash memory, and can solve problems such as prolonging the erasing operation time

Active Publication Date: 2020-03-13
WINBOND ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, reducing the erase size will increase the time for each erase operation

Method used

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Embodiment Construction

[0021] In order to make the above objects, features and advantages of the present invention more comprehensible, a preferred embodiment will be described in detail below together with the accompanying drawings.

[0022] figure 1 is a memory device according to an embodiment of the present invention. refer to figure 1 , the memory device 1 includes a memory array 10 , an address decoder 11 , a write / read circuit 12 , and a controller 13 . The memory array 10 includes a plurality of word lines WL0-WLX, a plurality of bit lines BLO-BLY, and a plurality of memory cells 100 arranged in a plurality of rows and a plurality of columns. The word lines WL0-WLX and the bit lines BL0-BLY are interleaved, and each memory cell 100 is coupled to a set of interleaved word lines and bit lines. These storage units 100 are divided into a plurality of sectors (sectors) S0-SN. Each sector S0-SN includes memory cells coupled to a predetermined number of word lines. For example, each sector S0-...

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Abstract

The invention provides a data wiping method applied to a memory device. According to the data wiping method, a word line group in a target sector is selected to serve as a target word line group according to the number of word lines; wiping operation is performed on a storage unit coupled to the target word line group through a wiping pulse; wiping verification is performed on storage units coupled to all bytes of a target word line in the target word line group; when it is judged that any storage unit fails in wiping verification, all bit lines are sequentially subjected to excessive wiping verification; when soft programming operation caused by non-passage of the excessive wiping operation is not executed, whether the number of the word lines is smaller than a maximum number is judged; and when it is judged that the number of the word lines is smaller than the maximum number, the number of the word lines is increased, and word line selection operation is executed again. Due to the fact that the adopted number of word lines for wiping operation is variable, the probability that wiping operation causes an electric leakage phenomenon can be lowered, and time needed for executing wiping operation can better conform to the operating state of the wiping operation.

Description

technical field [0001] The present invention relates to a data erasing method, in particular to a data erasing method for flash memory. Background technique [0002] Generally speaking, when flash memory (such as NOR flash memory) executes an erase operation, a post-program operation is performed to eliminate the electric leakage phenomenon on the bit line caused by the over-erase of the erase operation. However, when the power of the system is turned off during erase or post-program operation, the leakage phenomenon may not be completely eliminated. Therefore, it has been developed to reduce the probability of electric leakage by reducing the erasing size of each sector (ie, the number of word lines corresponding to one data erasing). For example, a sector includes 16 word lines, and each erasing of data is accomplished through 4 word lines. In this way, the erasing operation of this sector needs to be implemented through 4 times of data erasing. However, reducing the er...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C16/14G11C16/34
CPCG11C16/14G11C16/345
Inventor 陈宗仁
Owner WINBOND ELECTRONICS CORP