Comparator and δς modulation circuit
A comparator and integrator technology, applied in the field of comparators to avoid performance deterioration
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[0037] Hereinafter, embodiments of the present invention will be described with reference to the drawings. figure 1 It is a circuit diagram showing the structure of the comparator according to the embodiment of the present invention. The comparator 1 of this embodiment takes differential analog input signals vp, vn and differential digital dither signals d0, d1 as inputs.
[0038]This comparator 1 is constituted by the following parts: a P-channel MOS transistor X1 for inputting an inverted input signal vn to a gate; a P-channel MOS transistor X2 for inputting a positive-inverted input signal vp to a gate; Vn is input to the P-channel MOS transistor X3 whose gate and source are connected to the source of the P-channel MOS transistor X1; the positive phase input signal vp is input to the gate, source and the source of the P-channel MOS transistor X2 The connected P-channel MOS transistor X4; the gate and drain are connected to the drain of the P-channel MOS transistor X1, and...
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