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Comparator and δς modulation circuit

A comparator and integrator technology, applied in the field of comparators to avoid performance deterioration

Active Publication Date: 2020-06-30
YAMATAKE HONEYWELL CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0008] However, in the prior art, the attenuation rate when converting the digital dither signal into an analog signal, that is, the signal level of the analog dither signal needs to be determined by trial and error
In addition, it is necessary to prepare a conversion circuit itself for converting from a digital jitter signal to an analog jitter signal, and there are problems in terms of circuit scale and cost.

Method used

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Embodiment Construction

[0037] Hereinafter, embodiments of the present invention will be described with reference to the drawings. figure 1 It is a circuit diagram showing the structure of the comparator according to the embodiment of the present invention. The comparator 1 of this embodiment takes differential analog input signals vp, vn and differential digital dither signals d0, d1 as inputs.

[0038]This comparator 1 is constituted by the following parts: a P-channel MOS transistor X1 for inputting an inverted input signal vn to a gate; a P-channel MOS transistor X2 for inputting a positive-inverted input signal vp to a gate; Vn is input to the P-channel MOS transistor X3 whose gate and source are connected to the source of the P-channel MOS transistor X1; the positive phase input signal vp is input to the gate, source and the source of the P-channel MOS transistor X2 The connected P-channel MOS transistor X4; the gate and drain are connected to the drain of the P-channel MOS transistor X1, and...

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Abstract

A comparator and delta sigma modulation circuit of the invention reduce the circuit scale of the comparator. The comparator (1) includes a differential amplifier (10) which outputs a signal corresponding to difference of differential input signals (vp, vn); and an offset generator (11) which enables offset voltage of the differential amplifier (10) to increase and decrease according to digital jitter signals (d0, d1). The differential amplifier (10) consists of a first differential pair of transistors (X1, X2) and a second differential pair of transistors (X3, X4) configured in parallel with the first differential pair of transistors (X1, X2), and the offset generator (11) consists of a third differential pair of transistors (X11, X12) which is in cascode connection with the second differential pair of transistors (X3, X4) and performs ON / OFF operation according to the digital jitter signals (d0, d1) .

Description

technical field [0001] The present invention relates to a comparator suitable for a ΔΣ type AD converter and the like, and a ΔΣ modulation circuit using the comparator. Background technique [0002] It is well known that in ΔΣ-type AD converters, when converting a DC input signal, noise with a specific frequency called "audio noise" is generated for a specific input signal, deteriorating conversion accuracy. This phenomenon occurs when the level ratio of the input signal and the reference signal is an integer ratio. [0003] Generally, an AD converter is a circuit block that expresses the ratio of an input signal to a reference signal to be compared with a digital signal. The ΔΣ AD converter has a so-called ΔΣ modulation circuit that outputs the ratio of the input signal to the reference signal as a density wave of a digital signal. The rear stage of the ΔΣ modulation circuit is equipped with a digital filter, and the digital value of multiple bits is obtained by averaging...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M3/00
CPCH03M3/39H03M3/494H03F3/45H03M3/332H03M3/458
Inventor 梶田徹矢加藤太一郎手岛纮明
Owner YAMATAKE HONEYWELL CO LTD