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Array substrate and its preparation method, display panel

A technology of array substrates and substrate substrates, which is applied in semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, instruments, etc., and can solve problems such as array substrate-related processes that need to be improved

Inactive Publication Date: 2020-02-21
BOE TECH GRP CO LTD +1
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] Therefore, the current array substrate-related processes still need to be improved

Method used

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  • Array substrate and its preparation method, display panel
  • Array substrate and its preparation method, display panel
  • Array substrate and its preparation method, display panel

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Embodiment Construction

[0085] The embodiments of the present invention are described in detail below, and those skilled in the art will understand that the following embodiments are intended to explain the present invention, and should not be regarded as limiting the present invention. Unless otherwise specified, in the following examples that do not explicitly describe specific techniques or conditions, those skilled in the art can carry out according to commonly used techniques or conditions in this field or according to product instructions. The reagents or instruments used were not indicated by the manufacturer, and they were all commercially available conventional products.

[0086] In one aspect of the present invention, the present invention provides an array substrate. refer to Figure 3a-8d , to describe the array substrate of the present invention in detail.

[0087] According to an embodiment of the present invention, the array substrate includes: a base substrate 100, a thin film trans...

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Abstract

The present invention proposes an array substrate, a preparation method thereof, and a display panel. The array substrate includes: a base substrate; a thin film transistor disposed on one side of the base substrate; a data line disposed on one side of the base substrate; connecting electrodes, The source and drain of the thin film transistor are electrically connected to the data line; wherein, the orthographic projection of the active layer of the thin film transistor on the base substrate is within the orthographic projection of the gate of the thin film transistor on the base substrate. In the array substrate proposed by the present invention, the projection of the active layer on the gate insulating layer falls within the projection of the gate on the gate insulating layer, and the connecting electrodes are used to connect the source and drain electrodes to the data lines, thereby reducing the active The problem of light leakage caused by the layer leaking out of the grid, thereby improving the display stability of the display panel composed of the array substrate.

Description

technical field [0001] The present invention relates to the field of display technology, in particular, the present invention relates to an array substrate, a preparation method thereof, and a display panel. Background technique [0002] In the current pixel design, in order to save costs, the scheme of reducing the number of masks (MASK) is generally adopted, that is, the source-drain electrode layer (SD) and the active layer (ACT) share a half-tone mask (HTM MASK) scheme, and this scheme has been used on many pixel designs. However, there will be ACT under the SD metal formed by HTM NASK, refer to Figure 1a ~ Figure 1d and figure 2 ,especially in figure 2 In the three channels shown (I, II, III), the active layer (Active) at the source and drain electrodes will leak out of the gate (gate). When illuminated (hv), refer to figure 2 , the characteristics of the active layer 400 outside the gate 200 will change, the holes at the source 500 will increase with the light,...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/12H01L23/552H01L21/77
CPCH01L23/552H01L27/1214H01L27/124H01L27/1259G02F1/1368G02F1/136286H01L27/1222H01L27/127
Inventor 臧鹏程高山徐元杰
Owner BOE TECH GRP CO LTD
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